Timing Constraints
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Thomas Donner
Sep 5, 2016, 12:06:04 PM9/5/16
to opencores-tri-mode eth MAC
Hi
I found this core on opencores.org. I was looking for an IP-core which I can use to adapt it to AXI-Stream-Interface and the interface of this core is not fare away from this.
As I synthesized the sources I´ve got several timing violations between the different registers in Vivado.
Is this normal? Should I sad some spezial constraints?
Kind regards
Thomas
I found this core on opencores.org. I was looking for an IP-core which I can use to adapt it to AXI-Stream-Interface and the interface of this core is not fare away from this.
As I synthesized the sources I´ve got several timing violations between the different registers in Vivado.
Is this normal? Should I sad some spezial constraints?
Kind regards
Thomas
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