Loopback

[michael....@googlemail.com]

Hi,
is it possible to simple loopback the Rx signals to Tx?
I want to send data via Ostinato to the FPGA. From there I want to connect Rx and Tx and then send back the data to PC. Wireshark should show me the packages.
At the moment it works fine for the first package.
But all following packages are not visible in Wireshark. To send and receive the next package I have to restart the core.
At the moment I have wired the signals as shown:

//user interface
 .Rx_mac_ra(),                      //out
 .Rx_mac_rd(1),                    //in
 .Rx_mac_data(rx_mac_data),//out
 .Rx_mac_BE(BE),                 //out
 .Rx_mac_pa(rx_mac_pa),       //out
 .Rx_mac_sop(rx_mac_sop),   //out
 .Rx_mac_eop(rx_mac_eop),   //out

 .Tx_mac_wa(tx_mac_wa_int),  //out
 .Tx_mac_wr(rx_mac_pa),         //in
 .Tx_mac_data(rx_mac_data),   //in
 .Tx_mac_BE(BE),//big endian  //in
 .Tx_mac_sop(rx_mac_sop),     //in
 .Tx_mac_eop(rx_mac_eop),     //in

Thank you

[Paul Bar]

Look at the "Line_loop_en" it may do what you need.

[michael....@googlemail.com]

@Paul Bar

Hi,
the specifications says that Line_loop_en connects the interface between the PHY and the MAC. But I want to connect the User-Interface.
(See Specifications on PDF site 21/29)
"If Line_loop_en =1 , the packet transmited to Phy will loopback to receive side.
This function is used for test purpose."

Thank you

[michael....@googlemail.com]

Is it possible that in
MAC_rs_ff.v
is an error?

There is
        SYS_wait_end:
            if (!Rx_mac_rd)
                Next_state_SYS  =SYS_idle;
            else
                Next_state_SYS  =Current_state_SYS;

And if the read enable signal Rx_mac_rd is high, it always stays at the current state.
I think that the bang is wrong at this place.
Can someone confirm that?

[Paul Bar]

Hi Michael,

I have simulated received and sent part today and it seams that Rx_mac_rd needs to be toggle at the end of each receive 32bits.

Here is what you need (I think)

always @ (posedge Clk_user or posedge Reset)
    if (Reset)
        Rx_mac_rd   <=0;
    else if(Rx_mac_ra&Rx_mac_rd==0)
        Rx_mac_rd   <=1;
    else
        Rx_mac_rd   <=0;

So at each positive edge of your user clock you test if read is available and if Rx_mac_rd is ALREADY up. If it is, it means it is reading. You turn Rx_mac_rd down so that at next user clock we can turn it up again to read another 4bytes.

I might be wrong, but I think it is how it works. (at least in the simulation).

[Xana]

Hi Paul,

Is this part of code helping the loop-back between Rx and Tx?

What is the line_loop_en for exactly?/

Thanks,
Xana