bug fixes, implementatien on virtex 6 and virtex 7.
Mark Kaper
Hi,
For my
graduation I have used this the tri-mode ethernet MAC. I have used it
on virtex-6 and virtex 7 fpga's. However the tech files don't work on
these platforms. I have changed the RAM to work on this platform's.
However the 10Mb/s and 100Mb/s don't work, because we only used the
1000Mb/s. Therefor I just replaced the clock multiplexer to a direct
path to the 125Mhz clock.
Just as wzap wrote https://groups.google.com/forum/#!topic/opencores-tri-mode-eth-mac/qV3hNhu-KQQ I also encountered the problem that the MAC stopes when you stop sending packets.
His fix did not worked for the clock speeds I used the MAC on. So if made an other solution, if have connected the empty flag of the fifo to the fifo control. Where I check if it empty before I start sending data to the GMII interface.
I finally found a bug in my version where packages with an odd packet length aren’t received on the user interface. While all even packets are receiving. I hadn’t time to check why this occurred. But is suspect there is somewhere a problem with a checksum.
I hope my changes and observations are useful for anyone.
Kind regards,
Mark Kaper
Paul Bar
Mahesh Dananjaya
is that bug "odd packet length aren’t received on the user interface" was existing in the original code base. Or was it raised after you made some changes to the original code.Can you please explain it. Because we are using the same code as yours and we also encounter the same problem of not receiving odd packet length.
regards,
Mahesh
Thomas Donner
Hi
Are there any updates for this files in between.
I also plan to use this core with Xilinx.
Maybe I change the Ethernet Dataports to AXI-Stream.
kind regards
Thomas