Generating a Xilinx dual-port BRAM for the tx/rx FIFO implementation (Artix7)

[dpaul]

HI,

Since I want to implement this MAC core in a Xilinx Artix7 device, so I must regenerate the dual-port BRAM Xilinx primitive for the Artix7 to be used as the tx/rx FIFOs.

I am using Vivado 2015.4 and using the 'IP Catalog' therein. My question is regarding the 'Port B' configuration. In the 'Port B Optional Output Registers' configuration part we have the options <Primitives Output Register> and <Core Output Register>. If none of these 2 are enabled then we have a 1 clk cycle Port-B read latency. Enabling any 1 of then adds another clk cycle latency and enabling both adds 2 more clk cycle latency-ies.

Can anyone advice what is the best configuration for the above in a Xilinx series 7 device?

Regards,
dp

[dpaul]

I think I got my answer after reading the datasheet Block Memory Generator v8.2, pg058-blk-mem-gen.pdf, see page 57.

User Configuration
--------------------------------------------------------------------------------
Algorithm                  :     Minimum_Area
Memory Type                :     Simple_Dual_Port_RAM
Port A Read Width          :     [36]
Port A Write Width         :     [36]
Memory Depth               :     [512]
Port B Read Width          :     [36]
Port B Write Width         :     [36]
----------------------------------------------------------------------------------
Block RAM resource(s) (18K BRAMs)    : [1]
Block RAM resource(s) (36K BRAMs)    : [0]
----------------------------------------------------------------------------------

I have enabled the check-box for the 'Primitive output Register'. This gives an additional clk cycle latency but reduce the impact of the clock-to-out delay of the primitives.
Since only 1 Block RAM resource is used so no MUX will be used to output of the block memory generator core. Hence I have not enabled the 'Core Output Registers' check-box option.

If anybody wishes to differ or finds with this, please share the opinion here! :-)