Dear Daniel,
Its a tri core MIPS based SoC, Heterogeneous Operating
Systems (App OS, RTOS & small foot print OS) running on the cores. The plan
of implementation of Microvisor is for resource management & data exchange
between the cores. Though we have HW IPC, it has limited shared memory,
what we are looking for a more reliable solution by using an embedded
Hypervisor.
There is a common SRAM of 1MB shared among the cores. As of now I cannot
reveal much details about the SoC.
Thanks,
Raghu Nandan Ravi
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