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[公告] 博士論文口試 呂佳翰 (2014/7/22)
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Jul 15, 2014, 11:51:34 AM7/15/14
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嚙瞎嚙諍大嚙褒賂蕭T嚙線嚙緹嚙褒系嚙調士嚙論歹蕭f嚙踝蕭
嚙踝蕭 嚙談：嚙篆嚙諄選蕭
嚙踝蕭伀訇癒G嚙踝蕭嚙瘤嚙碼嚙請梧蕭
嚙篆嚙調委嚙踝蕭G
嚙調外嚙瘦嚙踝蕭嚙踝蕭嚙磐嚙請授、嚙踝蕭嚙窮嚙褓教授、嚙踝蕭嚙稿嚙請授、嚙踝蕭嚙瞑嚙褕教梧蕭
嚙調歹蕭嚙瘦嚙踝蕭嚙瘤嚙碼嚙請授、嚙踝蕭嚙蝓欽教授、嚙踝蕭嚙緙嚙罵嚙請梧蕭
嚙踝蕭 嚙踝蕭嚙瘦103 嚙羯 7 嚙踝蕭 22 嚙踝蕭 (嚙瞑嚙踝蕭嚙瘦) 14:00 - 16:00
嚙窮 嚙瘢嚙瘦嚙踝蕭q嚙稽 550 嚙罵議嚙踝蕭
嚙瘩 嚙諍：Register allocation issues on highly distributed
register file architectures
嚙論歹蕭K嚙緯嚙瘦
Embedded processors developed within the past few years have employed novel
hardware designs to reduce the ever-growing complexity, power dissipation,
and die area. While using a distributed register file architecture is
considered to have less read/write ports than using traditional unified
register file structures, it presents challenges in compilation techniques
to generate efficient codes for such architectures. Digital signal processors
(DSPs) with very long instruction word (VLIW) data-path architectures are
increasingly being deployed on embedded devices for multimedia processing
applications. To reduce the power consumption and design cost of VLIW DSP
processors, distributed register files and multi-bank register architectures
are being adopted to reduce the number of read and write ports associated
with register files, which presents new challenges for devising compiler
optimization schemes. Distributed register file architectures divide registers
into multiple sets, and it leads to complicated communication and small
register files. Complicated communication requires a new phase to handle it.
Small register files increase spilling and reduce performance. The
dissertation attempts to resolve theses two issues. There are three primary
results:
- A heuristic method is proposed for global register file assignment making
suitable decisions based on local register file assignment.The experimental
results indicates that the compilation based on our proposed approach
delivers performance improvements.
- We address the issues of reducing the spill cost for a VLIW DSP with
distributed register files.Spill code produced by register allocation is
traditionally handled by memory spills, but the multibank register-file
architecture provides the opportunity to spill-out register values onto
different register banks. We present a framework to model the live ranges in
different register banks, and treats register banks as optional spilling
locations.
- To reduce spilling possibly produced from the phase of register file
assignment, we propose a method which attempts to improve spilling by
estimating the spilling cost from two aspects: assignment and spilling. We
report that the SPIFR method not only reduces spilling ratios but increases
the performances.
The results of all experiments performed using our optimizing compiler based
on the Open64. The results of experiments showed the effectiveness of each of
my methods.
嚙諛作嚙瘠嚙踝蕭G
Journal Papers
1. Chia-Han Lu, Wen-Li Shih, Chung-Ju Wu, and Jenq Kuen Lee, "Achieving
Spilling-Friendly Register File Assignment for Highly Distributed Register
Files," Journal of Supercomputing, Accepted.
2. Chung-Ju Wu, Chia-Han Lu, and Jenq Kuen Lee, "Register Spilling via
Transformed Interference Equations for PAC DSP Architecture," Concurrency
and Computation: Practice and Experience, Volume 26, Issue 3, pages
779嚙碾799, 10 March 2014.
3. Chia-Han Lu, Yung-Chia Lin, Yi-Ping You, and Jenq Kuen Lee, "LC-GRFA:
global register file assignment with local consciousness for VLIW DSP
processors with non-uniform register files,嚙踝蕭 Concurrency and Computation:
Practice and Experience, Volume 21, Issue 1, Pages 101-114, Wiley, January
2009.
4. Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You,
Ya-Chaio Moo, and Jenq-Kuen Lee, "Effective Code Generation for Distributed
and Ping-Pong Register Files: a Case Study on PAC VLIW DSP Cores," Journal
of VLSI Signal Processing Systems, Volume 51, Number 3, pp. 269-288,
Springer, June 2008.
Conference Papers
1. Chung-Ju Wu, Chia-Han Lu, and Jenq Kuen Lee, "Expression Rematerialization
for VLIW DSP Processors with Distributed Register File," Compilers for
Parallel Computing 2009, Zurich, Switzerland, Jan. 2009.
2. Chia-Han Lu, Yung-Chia Lin, Yi-Ping You, and Jenq Kuen Lee, "A
Local-Conscious Global Register Allocator for VLIW DSP Processors with
Distributed Register Files," Compilers for Parallel Computing 2007,
Lisbon, Portugal, July 9-11, 2007.
Patents
1. Jenq-Kuen Lee, Chung-Ju Wu, Chia-Han Lu,"Spilling Method in Register Files
for Microprocessors," USA Patent, Application No.12/829,711, 2013.
2. Jenq-Kuen Lee, Chung-Ju Wu, Chia-Han Lu, "嚙畿嚙緲嚙踝蕭嚙踝蕭嚙誕用暫存嚙踝蕭嚙褕案迎蕭嚙踝蕭嚙碼嚙踝蕭
嚙糊," Taiwan Patent, Application No.098122720.
--
[;32m嚙踝蕭 Origin: 嚙踝蕭嚙踝蕭嚙賣站<bbs.cs.nthu.edu.tw>
[;32m嚙踝蕭 From: sagi1210 @ 114-37-159-46.dynamic.hinet.net [m
[;36msagi1210 嚙踝蕭 2014/07/15 Tue 23:52:10 嚙緬 114-37-159-46.dynamic.hinet.net 嚙論改蕭 [m
嚙踝蕭 嚙談：嚙篆嚙諄選蕭
嚙踝蕭伀訇癒G嚙踝蕭嚙瘤嚙碼嚙請梧蕭
嚙篆嚙調委嚙踝蕭G
嚙調外嚙瘦嚙踝蕭嚙踝蕭嚙磐嚙請授、嚙踝蕭嚙窮嚙褓教授、嚙踝蕭嚙稿嚙請授、嚙踝蕭嚙瞑嚙褕教梧蕭
嚙調歹蕭嚙瘦嚙踝蕭嚙瘤嚙碼嚙請授、嚙踝蕭嚙蝓欽教授、嚙踝蕭嚙緙嚙罵嚙請梧蕭
嚙踝蕭 嚙踝蕭嚙瘦103 嚙羯 7 嚙踝蕭 22 嚙踝蕭 (嚙瞑嚙踝蕭嚙瘦) 14:00 - 16:00
嚙窮 嚙瘢嚙瘦嚙踝蕭q嚙稽 550 嚙罵議嚙踝蕭
嚙瘩 嚙諍：Register allocation issues on highly distributed
register file architectures
嚙論歹蕭K嚙緯嚙瘦
Embedded processors developed within the past few years have employed novel
hardware designs to reduce the ever-growing complexity, power dissipation,
and die area. While using a distributed register file architecture is
considered to have less read/write ports than using traditional unified
register file structures, it presents challenges in compilation techniques
to generate efficient codes for such architectures. Digital signal processors
(DSPs) with very long instruction word (VLIW) data-path architectures are
increasingly being deployed on embedded devices for multimedia processing
applications. To reduce the power consumption and design cost of VLIW DSP
processors, distributed register files and multi-bank register architectures
are being adopted to reduce the number of read and write ports associated
with register files, which presents new challenges for devising compiler
optimization schemes. Distributed register file architectures divide registers
into multiple sets, and it leads to complicated communication and small
register files. Complicated communication requires a new phase to handle it.
Small register files increase spilling and reduce performance. The
dissertation attempts to resolve theses two issues. There are three primary
results:
- A heuristic method is proposed for global register file assignment making
suitable decisions based on local register file assignment.The experimental
results indicates that the compilation based on our proposed approach
delivers performance improvements.
- We address the issues of reducing the spill cost for a VLIW DSP with
distributed register files.Spill code produced by register allocation is
traditionally handled by memory spills, but the multibank register-file
architecture provides the opportunity to spill-out register values onto
different register banks. We present a framework to model the live ranges in
different register banks, and treats register banks as optional spilling
locations.
- To reduce spilling possibly produced from the phase of register file
assignment, we propose a method which attempts to improve spilling by
estimating the spilling cost from two aspects: assignment and spilling. We
report that the SPIFR method not only reduces spilling ratios but increases
the performances.
The results of all experiments performed using our optimizing compiler based
on the Open64. The results of experiments showed the effectiveness of each of
my methods.
嚙諛作嚙瘠嚙踝蕭G
Journal Papers
1. Chia-Han Lu, Wen-Li Shih, Chung-Ju Wu, and Jenq Kuen Lee, "Achieving
Spilling-Friendly Register File Assignment for Highly Distributed Register
Files," Journal of Supercomputing, Accepted.
2. Chung-Ju Wu, Chia-Han Lu, and Jenq Kuen Lee, "Register Spilling via
Transformed Interference Equations for PAC DSP Architecture," Concurrency
and Computation: Practice and Experience, Volume 26, Issue 3, pages
779嚙碾799, 10 March 2014.
3. Chia-Han Lu, Yung-Chia Lin, Yi-Ping You, and Jenq Kuen Lee, "LC-GRFA:
global register file assignment with local consciousness for VLIW DSP
processors with non-uniform register files,嚙踝蕭 Concurrency and Computation:
Practice and Experience, Volume 21, Issue 1, Pages 101-114, Wiley, January
2009.
4. Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You,
Ya-Chaio Moo, and Jenq-Kuen Lee, "Effective Code Generation for Distributed
and Ping-Pong Register Files: a Case Study on PAC VLIW DSP Cores," Journal
of VLSI Signal Processing Systems, Volume 51, Number 3, pp. 269-288,
Springer, June 2008.
Conference Papers
1. Chung-Ju Wu, Chia-Han Lu, and Jenq Kuen Lee, "Expression Rematerialization
for VLIW DSP Processors with Distributed Register File," Compilers for
Parallel Computing 2009, Zurich, Switzerland, Jan. 2009.
2. Chia-Han Lu, Yung-Chia Lin, Yi-Ping You, and Jenq Kuen Lee, "A
Local-Conscious Global Register Allocator for VLIW DSP Processors with
Distributed Register Files," Compilers for Parallel Computing 2007,
Lisbon, Portugal, July 9-11, 2007.
Patents
1. Jenq-Kuen Lee, Chung-Ju Wu, Chia-Han Lu,"Spilling Method in Register Files
for Microprocessors," USA Patent, Application No.12/829,711, 2013.
2. Jenq-Kuen Lee, Chung-Ju Wu, Chia-Han Lu, "嚙畿嚙緲嚙踝蕭嚙踝蕭嚙誕用暫存嚙踝蕭嚙褕案迎蕭嚙踝蕭嚙碼嚙踝蕭
嚙糊," Taiwan Patent, Application No.098122720.
--
[;32m嚙踝蕭 Origin: 嚙踝蕭嚙踝蕭嚙賣站<bbs.cs.nthu.edu.tw>
[;32m嚙踝蕭 From: sagi1210 @ 114-37-159-46.dynamic.hinet.net [m
[;36msagi1210 嚙踝蕭 2014/07/15 Tue 23:52:10 嚙緬 114-37-159-46.dynamic.hinet.net 嚙論改蕭 [m
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