[公告] 博士論文口試 陳福偉 (2013/11/25)

[fuwei]

清華大學資訊工程學系博士論文口試
學 生：陳福偉
指導教授：黃婷婷 教授
口試委員：
校內：黃婷婷 教授、王廷基 教授、麥偉基 教授
校外：黃俊達 教授、李進福 教授
時 間：102 年 11 月 25 日 (星期一) 10:00 - 12:00
地 點：資電館 447 會議室
題 目：Yield Improvement and High-Performance Design in 3-D Integrated Circuit

論文摘要：
With the advances of VLSI design technology, yield loss, manufacturing cost,
and reliability are more and more important. To tackle these issues, the
yield improvement, cost reduction, and reliability mechanisms methodologies
are required. In this dissertation, X-identification method, re-use methodology, and architecture of fault tolerance are proposed to achieve these goals.

First, to reduce the yield loss in high-performance design, a
physical-location-aware X-identification method is presented. To guarantee
that an application specific integrated circuit (ASIC) meets its timing
requirement, at-speed scan testing becomes an indispensable procedure for
verifying the performance of ASIC. However, at-speed scan test suffers the
test-induced yield loss. Because the switching-activity in test mode is much
higher than that in normal mode, the switching-induced large current drawn
causes severe IR drop and increases gate delay. X-filling is the most
commonly used technique to reduce IR-drop effect during at-speed test.
However, the effectiveness of X-filling depends on the number and the
characteristic of X-bit distribution. In this dissertation, we propose a
physical-location-aware X-identification which re-distributes X-bits so that
the maximum switching-activity is guaranteed to be reduced after X-filling.

Second, a clock tree algorithm with methodology of reuse in 3-D IC is
proposed. IP reuse methodology has been used extensively in SoC (System on
Chip) design. In this reuse methodology, while design and implementation cost
is saved, manufacturing cost is not. To further reduce the cost, this reuse
concept has been proposed at mask and die level in three-dimension integrated
circuit (3D IC). In order to achieve manufacturing reuse, in this dissertation, we propose a new methodology to design a global clock tree in
3D IC. The objective is to extend an existing clock tree in 2D IC to 3D IC
taking into consideration the wirelength, clock skew and the number of TSVs.

Finally, an architecture of TSV recovery by using test elevator TSV is
proposed. In order to increase the yield of 3-D IC, fault-tolerance technique
to recover failed TSV is essential. In this dissertation, an architecture of
TSV recovery by using test elevator TSV is proposed. With the architecture,
no spare TSV is required to be inserted in advance. Hence, no extra area
incurs. TSV assignment algorithm based on min-cost maximum-flow is proposed
taking into consideration the locations of functional TSV as well as test
TSV, so that the total Half-Perimeter Wire Length (HPWL) of a 3-D IC design
is effectively reduced.

Publication:

Jounal paper

Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin and TingTing Hwang, “A
Physical-Location Aware X-bit Redistribution for Maximum IR-Drop Reduction,”
IEEE Transactions on VLSI Systems 20(12): 2255-2264, 2012. (SCI)

Fu-Wei Chen and TingTing Hwang, “Clock Tree Synthesis with Methodology of
Re-Use in 3-D IC”, to be published in ACM Journal on Emerging Technologies
in Computing Systems (accepted) (SCI)

Conference paper

Fu-Wei Chen, Hui-Ling Ting and TingTing Hwang, ‘‘Fault-tolerant TSV by
Using Scan-chain Test TSV’’ to be accepted in Proceedings of ACM/IEEE Asia
and South Pacific Design Automation Conference (ASP-DAC), 2014

Fu-Wei Chen and TingTing Hwang, “Clock Tree Synthesis with Methodology of
Re-Use in 3-D IC,” to appear in Proceeding of ACM/IEEE Design Automation
Conference (DAC), 2012

Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin and TingTing Hwang, “A
physical-location-aware fault redistribution for maximum IR-drop reduction,”
in Proceedings of ACM/IEEE Asia and South Pacific Design Automation
Conference (ASP-DAC), pp. 701-706, 2011.
--
▄ ◢ ▄▄▄ ▄▄▄ ▄ ▄▄▄ [1;37m 清大資工 [m
[1;37;44m █ █◣◢█ █▄█ █▄█ █ █▄▄ [33mfuwei [37m 從 [33m 61.231.116.23 [m
█ █◥◤█ █ █ █ █▄▄ █▄▄ [1;37m【楓橋驛站】 telnet://imaple.tw [m
[;36mfuwei 於 2013/11/19 Tue 23:14:58 從 61-231-116-23.dynamic.hinet.net 修改 [m