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Dulce Donten
Some highly recommended introductory books for learning electronic devices and circuits include "The Art of Electronics" by Paul Horowitz and Winfield Hill, "Microelectronic Circuits" by Adel S. Sedra and Kenneth C. Smith, and "Electronic Devices and Circuit Theory" by Robert L. Boylestad and Louis Nashelsky. These books provide a solid foundation in the basics of electronics and circuit design.
For understanding digital electronics, "Digital Design" by M. Morris Mano and Michael D. Ciletti, "Digital Fundamentals" by Thomas L. Floyd, and "Digital Electronics: Principles and Applications" by Roger L. Tokheim are some of the best choices. These books cover the essential concepts and applications of digital electronics in a clear and comprehensive manner.
Yes, "Principles of Electronics" by V.K. Mehta and Rohit Mehta, and "Electronic Principles" by Albert Malvino and David J. Bates are excellent books that cover both analog and digital electronics comprehensively. These books provide a balanced approach to learning both fields, making them suitable for students and professionals alike.
"Practical Electronics for Inventors" by Paul Scherz and Simon Monk is a fantastic book for practical circuit design and hands-on learning. It offers a wealth of practical information, tips, and projects that help readers apply theoretical knowledge to real-world applications.
Yes, there are several online resources and e-books available for learning electronic devices and circuits. Websites like Coursera, edX, and Khan Academy offer courses and materials on electronics. Additionally, "Circuit Analysis and Design" by Fawwaz T. Ulaby and Michel M. Maharbiz is available as an e-book and provides a comprehensive guide to electronic circuits and devices.
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Flexible electronics has significantly advanced over the last few years, as devices and circuits from nanoscale structures to printed thin films have started to appear. Simultaneously, the demand for high-performance electronics has also increased because flexible and compact integrated circuits are needed to obtain fully flexible electronic systems. It is challenging to obtain flexible and compact integrated circuits as the silicon based CMOS electronics, which is currently the industry standard for high-performance, is planar and the brittle nature of silicon makes bendability difficult. For this reason, the ultra-thin chips from silicon is gaining interest. This review provides an in-depth analysis of various approaches for obtaining ultra-thin chips from rigid silicon wafer. The comprehensive study presented here includes analysis of ultra-thin chips properties such as the electrical, thermal, optical and mechanical properties, stress modelling, and packaging techniques. The underpinning advances in areas such as sensing, computing, data storage, and energy have been discussed along with several emerging applications (e.g., wearable systems, m-Health, smart cities and Internet of Things etc.) they will enable. This paper is targeted to the readers working in the field of integrated circuits on thin and bendable silicon; but it can be of broad interest to everyone working in the field of flexible electronics.
where k is the proportionality constant arising from above stated assumption. Normalizing Eq. (1) with respect to the proportionality constant, the normalized transit frequency can be written as:
Thus, the fTnorm is directly proportional to the mobility and inversely to square of channel length when the devices have similar parameters other than the mobility and the channel length. Putting the and L values from some of the recent works in Eq. (2), the comparison in Table 1 shows that the monocrystalline silicon based devices with channel length in nanoscale regime will have high fTnorm and as a result they will outperform most of the other semiconductor materials. Interestingly, the devices from high mobility materials such as graphene, carbon nanotubes,7 and some the 2D materials are slower than silicon. Clearly, the channel length or device technology plays a significant role in the final performance of devices. Therefore, instead of fixating on high-mobility materials, a holistic view with inputs from both material science and engineering is important. With technological advances, the devices from high mobility materials such as graphene, and carbon nanotube etc. could eventually catch up and possibly may have better performance than monocrystalline silicon, but this is unlikely in next few year as related technology is still in the nascent stage of development and is far from commercialization.8,9 Considering these facts, the monocrystalline silicon appears to be the best bet to meet immediate high-performance needs of flexible electronic systems. This also explains why silicon and other materials such as compound semiconductors have attracted significant interest in recent years. Nanostructures such as nanomembranes, nanoribbons, nanowires etc. from these materials have been explored for flexible electronics.10,11,12 Considering the challenges such as printing of aligned nanostructures, poor density of printed nanostructures, and difficulties in terms of obtaining very large-scale functional integrated circuits (ICs), the silicon-based microelectronics is an obvious choice.
The technology readiness to obtain devices down to nanoscale dimensions and the possibility to exponentially scale the device densities up to billions of devices per mm2, makes silicon based microelectronics a good candidate for addressing immediate high-performance needs in flexible electronics. For this the first issue that need to be overcome is the lack of flexibility (and hence conformability) of silicon wafers. This has been achieved by thinning the wafers down to
Given the wide scope of UTCs, a comprehensive review of various technological and applied aspects will complement several other reviews that have mainly focussed on organic semiconductors and their processing techniques such as printing or vacuum deposition etc.16,17,18 A few review articles have also discussed layer transfer processes and thin film silicon for solar cells.19,20 Related to UTCs, only a few review articles have been published and they have covered limited areas such as wafer thinning methods such as back grinding and integration on flexible substrate using stretchable interconnects.21,22,23,24 The analysis of UTCs covering topics such as changes in electrical-mechanical-optical-thermal properties, packaging, and stress-induced response variations, and comparison of various thinning methods has not been reported thus far. The in-depth analysis presented in this paper fills the above gaps in the literature and provide a complete overview of the research related to UTCs.
The thinning process impacts the mechanical properties of thinned electronic substrate. For example, during thinning by back grinding, the sub-surface damage (SSD) and deep cracks in Si result in poor bendability and eventually lead to early breakage of UTCs. Likewise, the etch pits and hillocks produced during thinning by wet etching could lead to localized stress and can decrease the breaking strength of Si. The localised stress or stress distribution at different locations in UTCs are typically studied with Finite Element Analysis29 and Micro-Raman Spectroscopy.30 The FEM analysis can provide an estimate of the residual stress at critical position like hinge and centre and the shift in Raman peak could provide deep insight into localised mechanical stresses.
Temperature is known to have significant impact on the performance and reliable operation of electronics and therefore discussion on thermal properties of UTCs gain importance. The heat dissipation, particularly in the UTCs realized from SOI wafers having top Si thickness in the nanoscale, significantly differ from conventional bulk Si based chips. For example, the thermal conductivity of
A wide range of technologies have been explored for realizing UTCs and a detailed discussion about some of are given in a few review articles.21,22 For the sake of completeness, the technologies involving either bulk Si wafer or SOI wafer are briefly discussed in this section. Figure 4 also gives a summary of these technologies, classified based on the fabrication stage at which the thinning is carried out. For example, when the thinning is carried out after the fabrication of electronic devices it is termed as post-processing, and when wafer undergoes some processing before the device fabrication then it is termed as pre-processing. Generally, the thinning is carried out after the device fabrication is completed. Following the discussion in previous section, the choice of technological approach to realize UTC requires careful consideration.
In post-processing approaches, the UTCs are typically obtained by physical removal of electronic substrate such as Si through either grinding, dry etching, chemical reaction or combination of these. In these techniques, the crystal structure of active Si area (for example, in the case of MOSFETs, the area up to well-depth) is unaffected and therefore their electrical response is at par with their bulk counterparts. However, as discussed in previous section the possibility of mechanical degradation cannot be ruled out. The techniques used as post-processing step can be broadly divided into: (i) grinding, (ii) dry etching, and (iii) layer transfer.
Some technologies for UTCs require processing of wafers before initiating the device fabrication. These steps are termed as pre-processing steps and the front-end fabrication follows thereafter. The techniques for realizing UTCs which require pre-processing are discussed below:
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