PBI protocol
Richard Andrews
This is the description for the 1090 expansion box of which a few got out
of Atari's warehouse. It does explain in further detail the parallel bus
protocol. The hardware specifications have been omitted They specified
such things as "contact fingers shall be plated with nickel of the low stress
type, Class II per federal specification....."ad nausem. Enjoy!
Rich Andrews
...ihnp4!chinet!cabbie
XL-Series expansion system
(edited)
Technical Specifications
Revision A
5/11/84
The expansion box is an extension device providing support
of expansion cards for the Atari computer line. This device provides
Atari systems with expansion and enhancement. Yhe bus enables the consumer
to connect a variety of differemt devices to the Expansion Box Interface
(E.B.I.). Some different devices are listed below.
1) RAM EXPANSION
2) SERIAL/PARALLEL INTERFACE
3) Z-80 PROCESSOR
4) 80 COLUMN VIDEO MONITOR INTERFACE
5) HOBBYIST PROTOTYPING CARD
Architectural Overview
The expansion box contains a triple output power supply providing
regulated +12 volts and -12 volts and +10 volts unregulated. Also
provided is a half wave rectified AC waveform (for power line frequency
reference only) and +5 volts (for reference only)
The address bus, data bus and control lines are buffered by the
expansion box and bussed to the five edge connectors provided.
Connector pin-out top view
+10V 1 2 +10V
AUDIO IN 4 3 EXTSEL
GND 6 5 EXTENB
MPD' 8 7 REF
IRQ' 10 9 RDY'
RESET' 12 11 AC
ABUFFSEL' 14 13 CARDSEL'
-12V 16 15 BR/W'
GND 18 17 A15
BPHASE2 20 19 A14
GND 22 21 A13
+5V REF 24 23 A12
Reserved 26 25 A11
Reserved 28 27 A10
Reserved 30 29 A9
DBUFSEL' 32 31 A8
D7 34 33 A7
D6 36 35 A6
D5 38 37 A5
D4 40 39 A4
D3 42 41 A3
D2 44 43 A2
D1 46 45 A1
D0 48 47 A0
+12V 50 49 COMPGNDRET
PIN DESCRIPTIONS
Pins 1,2 +10V +10 volts unregulated
Pin 3 EXTSEL External Select (Input) ==> This open collector line is
generated internally by the Expansion Box Device (E.B.D.).
This signal should be active low whenever EXTENB is active and
the E.B.D. is selected and there is a valid E.B.D. address
on the bus. EXTSEL' causes a CAS' inhibit on the main board
allowing a remapping process. Although E.B.D. can be mapped
in any valid ram location, these devices shoudl follow the
ATARI guidelines for E.B.D. locations so that future ATARI
devices can be used. The drive desice should be capable of
sinking 10 ma.
Pin 4 Audio Audio In (Input) ==> This line is tied directly to the
audio summation network of the computer. The audio signal
input is 100mv peak to peak with a 4.7K ohm load impedance.
Pin 5 EXTENB External Decoder Enable (Output) ==> This output goes high when
there is a valid RAM access. Any E.B.D. can map during a
valid EXTENB but the E.B.D. should only map in accordance
to specified address locations.
Pin 6 GND Ground
Pin 18 GND Ground
Pin 22 GND Ground
Pin 7 REF' Refresh (Output) ==> This output can be used for refresh
timing on dynamic memories connected to the E.B.I.
Pin 8 MPD' Math Pack Disable (Input) ==> This open collector input is
sed to diable the math pack of the OS ROM ($D800-$DFFF).
This should be done when the E.B.D. is deselected and has
a handler resident. The driving device should be capable
of sinking 10ma.
Pin 9 RDY Ready (Input) ==> This open collector input signal allows
the E.B.D. to halt the microprocessor ONLY during read cycles.
Driving this input low will extend the read cycle for slow
peripherials. The sinking device should be capable of sinking
10ma.
Pin 10 IRQ' Interrupt Request (Input) ==> This open collector line
creates an interrupt on the microprocessor. The interrupt
can then invoke the handler ROM or other service routines
for the E.B.D. The driving device should be capable of sinking
10 ma.
Pin 11 AC The half-wave rectified AC signal from the power supply
bridge (rectifier). May be used as an unfiltered line
frequency reference.
Pin 12 RESET Reset (Output) ==> Reset is an active low signal that
occurs either on power-up or by depressing the reset key
on the computer.
Pin 14 ABUFFSEL Buffer Select (Input) ==> This signal, when driven high
disables (tri-states) the address lines from the computer.
Pin 13 CARDSEL (Output) ==> This signal enables the E.B.D. to respond to
the hardware protocol. In the 1090 it will always be grounded.
In future Atari products it will be an address space select
line for processors which have an address space in excess of
64K.
Pin 15 BR/W Buffered Read/Write (Output) ==> This output is active high
for a read cycle and active low for a write cycle.
Pin 16 -12V -12 Volts, Regulated
Pin 20 BPHASE2 Buffered Phase 2 Clock (Output) ==> This clock output line is
a buffered phase 2 clock from the processor.
Pin 24 +5VREF This is a +5 volt regulated reference. Expansion cards should
not draw more that 10ma maximum from this reference.
Pins 26,28,20 Reserved for future use.
Pin 32 DBUFSEL' Data Buffer Select (input) ==> This signal, when driven low
enables the data bus transcievers for data to and from the
computer.
Pin 49 COMPGNDRET Computer ground return is a ground connction only through
the flat cable connector and is otherwise isolated.
Pin 50 +12V +12 volts regulated
Interface Reqirements
All E.B.I. outputs have the drive capability of 24ma at logic 0
and -6ma at logic 1
All E.B.I. open collector input lines must be able to sink 10ma
minimum at .4 volts (max).
All E.B.I. non open collector input lines except AUDIO must have the
capability of driving 24 ma at logic 0 and -6 ma at login 1.
All E.B.I. signals except audio will be standard TTL logic levels.
The AUDIO input line must drive a 4.7 KOhm source impedence with
100mv peak to peak signal.
Each expansion box card should not load any E.B.I. output with
more that three standard TTL loads.
Hardware Device Protocol
The E.B.D.'s have the following charcteristics:
1) The interface between the E.B.D. and the CPU is defined through
the handler/OS resident is the OS ROM. The OS can support 8 devices at one
time with only one enabled during any given interval.
2) Every E.B.D. has a unique handler that resides in the CPU memory
from $D800-$DFFF. The ROMs containing the code for these handlers are
physically resident on the respective E.B.D.s. To access this handler, the
math pack must be disabled with MPD. When the Math pack is disabled (this
should happen whenever the E.B.D. is selected and has an external handler)
the computer will generate EXTENB for the math pack area. The E.B.D. must
then generate the correct EXTENB/EXTSEL protocol. If the device does not
generate EXTSEL the CPU will access (in the 64K computers) an unused area of
RAM. This area should not be used since all computers of this series do not
have that area of RAM.
3) The location $D1FF in the CPU memory map is reserved for passing control
information between the CPU and the E.B.D.'s. The CPU selects one of the
devices by writing a "1" into the desired bit in location $D1FF. The
device can be deselected by writing a "0" into the desired bit. The CPU
can access 8 devices, but only one of the devices may be active at a time.
If the IRQ line is pulled low the CPU can read status for location $DIFF and
locate the requesting E.B.D. If the bit is a "0" the device has not caused
the interrupt. The E.B.D. must clear the interrupt flag when the interrupt
is being serviced.
4) An E.B.D. should assert MPD only when it is selected. An E.B.D.
should assert EXTSEL only when it is selected and if EXTENB is asserted.
5) An E.B.D. may respond to any selects D0 through D7. It is
recommended that the E.B.D's have configuration switches to allow them
to respond to any one of the selects. Some of the computer systems use the
E.B.I. to support internal devices; therefore the user should check each manual
for device locations. If the system has devices in specific locations, those
are reserved in that computer. (1450 modem and speech synthesizer)
6) An E.B.D. handler may respond to addresses in the region
$D800-$DFFF only when it is selected.
7) A peripheral may respond to addresses in the region $D100-$D1AF
only when selected.
8) The E.B.D.'s will have priority over the SIO peripherials when
they are addressed generically.
9) The CPU address space from $D600 TO $D7FF is reserved for E.B.I.
devices as follows:
Device Range Size
--------------------------------------------------------------------------
D0 $D600-$D61F 32 bytes
$D620-$D63F Rerserved (modems)
D1 $D640-$D67F 64 bytes
D2 $D680-$D6BF 64 bytes
D3 $D6C0-$D6FF 64 bytes
D4 $D700-$D73F 64 bytes
D5 $D740-$D77F 64 bytes
D6 $D780-$D7BF 64 bytes
D7 $D7C0-$D7FF 64 bytes
The 800XL will not provide CPU RAM in this address space. The
600XL has no internal RAM in this address space. The 1450XL does allow access
to internal RAM in this address space. E.B.D.'s should provide this RAM on
the E.B.D. or be restricted for use only on the 1450XL.
RAM 64KMR
The RAM 64KMR module is designed to be used in the expansion box.
However, it does not completly adhere to the E.B.I. protocol since
it will allow RAM to be selected in liew of the OS.(when used in the 1064
mode)
RESERVED MEMORY LOCATIONS
The memory space from $D100 to $D1AF is available for use by most
applications. This space should be used by a device with the device select
bit enabling it's use. If the device select bit is not used, there is
potential bus conflict between E.B.D.'s. The remainder of the I/O space
between $D1B0 and $D1FF is mapped as follows:
$D1B0-D1C7 Speech/Modem/Disk Registers
$D1C8-$D1CE Atari Reserved
$D1CF Alternate Interrupt Register (1450 only)
$D1D0-$D1DF Audio Registers
$D1E0-$D1E7 Atari Reserved
$D1E8-$D1EF Parrallel/Serial Registers
$D1F0-$D1F7 Alternate CPU Registers
$D1F8-$D1FD 80 Column Video Registers
$D1FE RAM Bank select Registers
$D1FF E.B.D. Select/Interrupt Register
<EOF>
Here line eater....eat THIS!
Richard Andrews
This is a re-post. I don't know if the original version got out. I
didn't see it. oh well.....