>Thanks for the post of the DSP56200. It is good to be able to read of
>new DSP chip architectures here in net.arch. I assume that the DSP56200
>is designed as a peripheral for the 56000.
>Table 1, listing the DSP56200 "performance figures" did not make any
>sense: It seems for a FIR filter application with, say, 32 taps,
>the maximum sampling frequency DECREASES as you add chips. This doesn't
>make any sense. Can anyone explain or correct?
thanks for catching this serious error in the table. the correction is
below.
TABLE I - DSP56200 Performance Figures
SINGLE CHIP
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| Maximum Sampling Frequency (KHz) |
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| | Number of Taps |
| Mode | 32 64 128 256 |
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| FIR Filter | 227 132 71 37 |
| Adaptive Filter | 123 69 37 19 |
| Dual FIR Filters | 122 68 36 * |
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FOUR CHIPS
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| Maximum Sampling Frequency (KHz) |
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| | Number of Taps |
| Mode | 128 256 512 1024 |
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| FIR Filter | 222 132 71 37 |
| Adaptive Filter | 120 69 37 19 |
--------------------------------------------
EIGHT CHIPS
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| Maximum Sampling Frequency (KHz) |
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| | Number of Taps |
| Mode | 256 512 1024 2048 |
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| FIR Filter | 204 132 71 37 |
| Adaptive Filter | 115 69 37 19 |
--------------------------------------------
SIXTEEN CHIPS
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| Maximum Sampling Frequency (KHz) |
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| | Number of Taps |
| Mode | 512 1024 2048 4096 |
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| FIR Filter | 175 132 71 37 |
| Adaptive Filter | 105 69 37 19 |
--------------------------------------------