Modelsim 10.1c Crack
0 views
Skip to first unread message
Luther Lazaro
Jun 15, 2024, 3:48:33 AM6/15/24
to neronapo
I am trying to run the specman environment with modelsim simulator. My source code is in VHDL. As per the example in cadence installatuion directory I did instantiate a specman component in vhdl testbench but still it's giving error in compilation time as:
Reply all
Reply to author
Forward
0 new messages