My Nixie Clock

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Jean-Pierre G

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Jun 17, 2018, 2:09:39 PM6/17/18
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Hi all,

Here is my nixie clock :
  • 6x IN14 russian tubes
  • 6x Neopixels Leds
  • 2x HV5530 high Voltage drivers
  • 1x 210V High Voltage step up power supply
  • 1x 5V step down power supply
  • 1x ESP32 microcontroller
  • 1x radar sensor
  • 1x light sensor
  • 1x (option) temperature + pression sensor
  • 2x home made pcbs

PCB.jpg 

And one Android application speaking to the ESP32 with Bluetooth Low Energy

Just add a piece of wood (from Vietnam) a CNC mill, a lot of hours

CNC_mill.jpg 

See it in action :

 

JP

gregebert

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Jun 18, 2018, 1:12:42 AM6/18/18
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The home-made PCBs look very good; I tried making my own more than 30 years ago and they were difficult to solder because the holes were not plated-thru and the tinning solution left the pads over-oxidized.

Nice to see a simplified design that can be built with a single-sided PCB.

Jean-Pierre G

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Jun 18, 2018, 7:36:57 AM6/18/18
to neoni...@googlegroups.com
Thank you !

I got this idea to stack two pcb because I wanted the neo pixels not
to be "jailed" into the nixies pins.
So due to this I needed two pcbs...
Finally it offers a lot a compacity in the design as the ESP32 and the
power supply have their own 2 sides pcbs .

2018-06-18 7:12 UTC+02:00, gregebert <greg...@hotmail.com>:
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Flynn Harrison

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Jun 18, 2018, 8:44:03 AM6/18/18
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im currently trying to do somthing simmiler with only 1 pcb, but ive been sort of stuck on the best method for my logic level conversion (3.3 to 12v) for the esp32 to HV shift register. so im wondering what method did you use, i.e MOSFET or BJT ect.. ?

Jean-Pierre G

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Jun 18, 2018, 8:46:14 AM6/18/18
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Simple mosfet + 2 resistors !


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Flynn Harrison

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Jun 18, 2018, 8:49:06 AM6/18/18
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thanks, did you use somthing like a BSS138?


On Monday, 18 June 2018 22:46:14 UTC+10, Jean-Pierre G wrote:
Simple mosfet + 2 resistors !


Le lun. 18 juin 2018 à 14:44, Flynn Harrison <fl...@belmontharrison.net> a écrit :
im currently trying to do somthing simmiler with only 1 pcb, but ive been sort of stuck on the best method for my logic level conversion (3.3 to 12v) for the esp32 to HV shift register. so im wondering what method did you use, i.e MOSFET or BJT ect.. ?

Jean-Pierre G

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Jun 18, 2018, 9:13:04 AM6/18/18
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Well I don't remember exactly... It's the smd version of 2N7000 n channel mosfet.
Or any other tiny mosfet !

Jean-Pierre G

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Jun 18, 2018, 2:31:49 PM6/18/18
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The exact reference is 2N7002  datasheet here : https://assets.nexperia.com/documents/data-sheet/2N7002.pdf (any manufacturer will be ok)

Jean-Pierre G

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Jun 18, 2018, 2:34:08 PM6/18/18
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and schematics (with another reference !)

image.png

Nick

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Jun 18, 2018, 7:06:41 PM6/18/18
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Rather than doing it all with discrete components, have a look at the TI TXB010x series of bidirectional level shifters.

They are cheap, come in a range of packaging including soic, and in various widths, i.e 2, 4, 6 or 8 channels.

Nice chip.

Nick

gregebert

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Jun 18, 2018, 7:07:21 PM6/18/18
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Be careful when cascading HV5532's. The datasheet does not specify a minimum propagation delay, but it DOES require a minimum hold-time of 10nsec. Even though the datasheet says you can cascade the data-out/data-in pins of multiple devices, there are no spec numbers to support this so the next-best thing is to route the clock signal in the opposite direction of the data. I suspect the minimum prop-delay of the data-out pin is at least 10nsec, but I cant prove it.

I tend to overdesign with paranoia and pessimism, so I actually use a separate clock pin for my HV5532's when I cascaded 2 of them, so there is no possibility of a timing issue as long as I sequence the clocks correctly. Also, my clock has a total of six HV5532's (I have 14 tubes) , but I dont cascade them into a single chain. Instead, I break them into 3 parallel chains and use a level-translator IC (MC14504) to shift from the 3.3V FPGA to 12V for the HV5532. It's been running flawlessly for 2-3 years now.

John Rehwinkel

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Jun 18, 2018, 7:22:19 PM6/18/18
to 'Grahame' via neonixie-l
> Rather than doing it all with discrete components, have a look at the TI TXB010x series of bidirectional level shifters.
>
> They are cheap, come in a range of packaging including soic, and in various widths, i.e 2, 4, 6 or 8 channels.

Those are handy chips (I've used 'em with a Raspberry Pi to drive LED matrices), but they're not suitable for 12V signals like these HV chips use.

- John

Nick

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Jun 18, 2018, 8:07:40 PM6/18/18
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True. What about the CD4504B? 20V tolerance.

Nick

John Smout

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Jun 19, 2018, 1:07:32 AM6/19/18
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I have just read about the 25% tax that Mr Trump is going to put on Chinese imports to the USA from July 6th. Most electronic components will be taxable.

What effect will this have on US manufactured electronic goods or the hobbyist? Will it delay the import of Chinese goods and how will the consumer pay the tax?

John S

gregebert

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Jun 19, 2018, 1:18:46 AM6/19/18
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A lot of the items I purchase via Ebay are labeled as "gifts" by the sender in China, so I suppose those might slip under the radar.

Jean-Pierre G

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Jun 19, 2018, 1:43:24 AM6/19/18
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Hi
Why do you take care of such a small propagation delay ?
I simply generate the clock with 10ms period. And it works like a charm with two hv5530 for 6 tubes.

JP

gregebert

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Jun 19, 2018, 2:12:21 AM6/19/18
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For setup time, I agree the 10ns is insignificant for a 10msec period. But for hold-time, the timing analysis starts and ends on the same clock edge. A positive hold time, in this case +10nsec, means that you must hold the data_in signal stable for 10nsec after the sampling-edge of clock, which is the falling-edge for the HV5530. If the data_in signal comes from a part that propagates in, say 7nsec, you would violate the hold-time spec by (10 - 7) = 3nsec. It may not sound like a lot of time, but hold-time violations are not forgiving. You should see what we do at my day job to fix a 25psec hold-time violation.

Another less-obvious source of timing difficulty is clock-skew; if the clock-delay to the receiving part is *longer* than the clock-delay to the sending part, the resulting difference in delay (clock-skew) worsens your hold-time. A common practice is to route clock and data signals in opposite directions.

As I said, I overdesign things. I've seen too many timing problems on PC boards and inside ICs causing failures that are very difficult to find and fix, so I always take the worst-possible operation for granted, and design around them.
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