US-MA Boston ASIC Physical Design Manager/Lead - Vitesse

[Vitesse Semiconductor]

Local candidates only. No agencies or contracts please.

Vitesse Semiconductor Corporation a leading supplier of high
performance integrated circuits (ICs) is looking to add Physical
Design expertise to its Boston location.

Email: porras@vitesse if you are interested in this opportunity.

The Manager of Physical Design/Lead is responsible for driving and
executing the backend methodology, determining product chip test
strategies and working closely with the Manager of Design from product
inception, synthesis through fabrication. Is also responsible for all
physical design schedules for products and will work proactively with
the other technical functional managers to ensure predictable and
timely delivery of these products.

Deliverables include floor planning, IO placement/pad ring, physical
synthesis, layout, cell placement/routing, static timing
analysis/closure techniques, power distribution, clock
distribution/balancing, APTG vectors, parasitic extraction, back
annotation and signal integrity analysis.

At least 7-11 years of deep sub-micron CMOS IC physical design.
Experience with chip top level, proven backend techniques, emerging
placement/layout methodology and DFT required. Exposure to logic
design and high speed IO highly desirable. An understanding of timing
driven design techniques, UNIX and scripting languages like TCL and
PERL.

Has knowledge of COT flow. Backend tools such as Magma, Primetime,
Simplex or Calibre is desirable. BS/MS degree or equivilent
experience.