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Kushal Vangara
,
Jiayuan Meng
2
11/8/15
Help please!! how to simulate multi caches using gem5?
Hi Kushal, Sorry, I'm no longer maintaining/suppoting MV5sim. You might want to email gem5_users
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Help please!! how to simulate multi caches using gem5?
Hi Kushal, Sorry, I'm no longer maintaining/suppoting MV5sim. You might want to email gem5_users
11/8/15
min cai
, …
Fereidoun Ahourai
4
10/13/15
Downloading mv5sim or opening http://www.cs.virginia.edu/~jm6dg/ encounters 403 error
I'm getting the same error now. Could you please help me to download it? Forbidden You don't
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Downloading mv5sim or opening http://www.cs.virginia.edu/~jm6dg/ encounters 403 error
I'm getting the same error now. Could you please help me to download it? Forbidden You don't
10/13/15
Hamid Reza Motaman
,
Jiayuan Meng
4
1/9/14
compile error
Hi SHRM, I'm actually not sure how Gem5 models energy, but I believe someone has integrated McPAT
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compile error
Hi SHRM, I'm actually not sure how Gem5 models energy, but I believe someone has integrated McPAT
1/9/14
Hamid Reza Motaman
1/8/14
compile error
Hi I get 2 error when I try to compile MV5 I would really appreciate if someone help me to fix it ./
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compile error
Hi I get 2 error when I try to compile MV5 I would really appreciate if someone help me to fix it ./
1/8/14
Vinay V.L
, …
Rohith Tenneti
8
11/1/13
compile error
Can't remember, do not have access to the machine we used to work on. If it helps, we contacted
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compile error
Can't remember, do not have access to the machine we used to work on. If it helps, we contacted
11/1/13
Eliseu Miguel
, …
Liang Wang
12
11/30/12
How to run example SMP
The workload I was investigated is HOTSPOT. Your suggestion on using SIMD with warpSize=1 to mimic
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How to run example SMP
The workload I was investigated is HOTSPOT. Your suggestion on using SIMD with warpSize=1 to mimic
11/30/12
Ankit Sethia
,
Jiayuan Meng
2
6/5/12
integration with mcpat
Hi Ankit, Unfortunately we haven't integrated mcpat yet. But maybe the same thing would work for
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integration with mcpat
Hi Ankit, Unfortunately we haven't integrated mcpat yet. But maybe the same thing would work for
6/5/12
Atie
,
Jiayuan Meng
3
6/1/12
How to find dependencies between cores
Hi Atie, Sorry, I was traveling during the last few weeks and I missed your email. pkt->req->
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How to find dependencies between cores
Hi Atie, Sorry, I was traveling during the last few weeks and I missed your email. pkt->req->
6/1/12
daniel tian
, …
Jiayuan Meng
34
3/24/12
Re: Could u please help checking the bottleneck?
I'm actually not quite familiar with M5's O3 core configuration. I would guess M5 have some
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Re: Could u please help checking the bottleneck?
I'm actually not quite familiar with M5's O3 core configuration. I would guess M5 have some
3/24/12
Eliseu Miguel
2
3/15/12
Question about mv5 Simulator
It was solved. Thanks On Mar 13, 10:53 pm, Eliseu Miguel <eliseumig...@gmail.com> wrote: >
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Question about mv5 Simulator
It was solved. Thanks On Mar 13, 10:53 pm, Eliseu Miguel <eliseumig...@gmail.com> wrote: >
3/15/12
Bin
,
Jiayuan Meng
2
3/6/12
How to interpret the statistics
Hi Bin, The documentation of the statistics is basically the text in the m5stats.txt... I know Gem5
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How to interpret the statistics
Hi Bin, The documentation of the statistics is basically the text in the m5stats.txt... I know Gem5
3/6/12
João Lucas
,
Jiayuan Meng
2
2/16/12
Problem runing MV5
Here is the environment that I'm using: GCC: 4.2.4 Python: 2.5.2 scons: 0.96.95 Some additional
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Problem runing MV5
Here is the environment that I'm using: GCC: 4.2.4 Python: 2.5.2 scons: 0.96.95 Some additional
2/16/12
Bin
,
Jiayuan Meng
3
1/7/12
can't compile MV5 version 0.9
This is mainly a compatibility issue. Postprocessing is not necessary. Jiayuan On Sat, Jan 7, 2012 at
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can't compile MV5 version 0.9
This is mainly a compatibility issue. Postprocessing is not necessary. Jiayuan On Sat, Jan 7, 2012 at
1/7/12
daniel.tian
,
Jiayuan Meng
17
1/5/12
About the SIMD core pin ticks
Did you try using 1 SIMD core? I'm thinking it could also be false sharing. Did you check the
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About the SIMD core pin ticks
Did you try using 1 SIMD core? I'm thinking it could also be false sharing. Did you check the
1/5/12
cecil
,
sahar guermazi
2
12/12/11
Installation Problem
Hi cecil, you can refer to this: http://groups.google.com/group/mv5sim/browse_thread/thread/
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Installation Problem
Hi cecil, you can refer to this: http://groups.google.com/group/mv5sim/browse_thread/thread/
12/12/11
cecil
,
Jiayuan Meng
2
12/11/11
Install MV5 on ubuntu 10.10
Should be okay. Please follow the quick start guide on our website. https://sites.google.com/site/
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Install MV5 on ubuntu 10.10
Should be okay. Please follow the quick start guide on our website. https://sites.google.com/site/
12/11/11
Vinay V.L
,
Jiayuan Meng
2
11/20/11
Multiple Workloads in SIMD cores
Hi Vinay, I'm not sure why the segmentation fault happened. Can you give me more details? Did you
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Multiple Workloads in SIMD cores
Hi Vinay, I'm not sure why the segmentation fault happened. Can you give me more details? Did you
11/20/11
Vinay
,
Jiayuan Meng
3
11/17/11
Cache Replacement policy and Cache Banks
Yes, in frCommon.py, you can see each cache class has a "repl" attribute. Actually in the
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Cache Replacement policy and Cache Banks
Yes, in frCommon.py, you can see each cache class has a "repl" attribute. Actually in the
11/17/11
daniel tian
,
Jiayuan Meng
2
11/17/11
About the ticks collect
Hi Daniel, First, sorry for the late reply... I'm having a conference this week. I'm not sure
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About the ticks collect
Hi Daniel, First, sorry for the late reply... I'm having a conference this week. I'm not sure
11/17/11
Ankita (Garg) Goel
,
Jiayuan Meng
4
11/12/11
Config file for simulating heterogeneous architecture
Another thing to try is to set localAddrPolicy to 0 instead of one, and then the simulator should use
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Config file for simulating heterogeneous architecture
Another thing to try is to set localAddrPolicy to 0 instead of one, and then the simulator should use
11/12/11
Ankita (Garg) Goel
,
Jiayuan Meng
6
11/11/11
Building the fractal api library
Thanks a lot Jiayuan! I could successfully build the fractal library and also the benchmarks. As you
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Building the fractal api library
Thanks a lot Jiayuan! I could successfully build the fractal library and also the benchmarks. As you
11/11/11
daniel.tian
,
Jiayuan Meng
2
11/7/11
About SIMD code
> Is the SIMD core based on > alpha ISA with additional SIMD instructions? or the SIMD code is
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About SIMD code
> Is the SIMD core based on > alpha ISA with additional SIMD instructions? or the SIMD code is
11/7/11
Ankita (Garg) Goel
,
Jiayuan Meng
8
11/4/11
Query regarding latest MV5
The fractal API is native to MV5. Actually it kind of drove MV5's early development. Thanks,
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Query regarding latest MV5
The fractal API is native to MV5. Actually it kind of drove MV5's early development. Thanks,
11/4/11
Rohith Tenneti
,
Jiayuan Meng
2
11/2/11
Assembly MODE=12
Yes, it's for generating the assembly code for benchmarks running over the simulator. Jiayuan On
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Assembly MODE=12
Yes, it's for generating the assembly code for benchmarks running over the simulator. Jiayuan On
11/2/11
daniel.tian
,
Jiayuan Meng
3
11/1/11
About the system Call
Thank you very much. On Tue, Nov 1, 2011 at 10:38 AM, Jiayuan Meng <meng.j...@gmail.com>
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About the system Call
Thank you very much. On Tue, Nov 1, 2011 at 10:38 AM, Jiayuan Meng <meng.j...@gmail.com>
11/1/11
daniel.tian
,
Jiayuan Meng
2
10/27/11
crosstool in MV5
Hi Xiaonan, This is probably because some download links in the script needs to be updated. FYI, the
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crosstool in MV5
Hi Xiaonan, This is probably because some download links in the script needs to be updated. FYI, the
10/27/11
daniel.tian
,
Jiayuan Meng
3
10/24/11
panic: Not all stats have been initialized
Thank you. I fixed it. On Oct 23, 9:25 pm, Jiayuan Meng <meng.jiay...@gmail.com> wrote: >
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panic: Not all stats have been initialized
Thank you. I fixed it. On Oct 23, 9:25 pm, Jiayuan Meng <meng.jiay...@gmail.com> wrote: >
10/24/11
Ankita (Garg) Goel
,
Jiayuan Meng
4
10/13/11
Error building X86_SE: ‘class X86ISA::DTB’ has no member named ‘flushAddr’
- In your experiments, what is the largest SIMD & OOO system configuration you could run without
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Error building X86_SE: ‘class X86ISA::DTB’ has no member named ‘flushAddr’
- In your experiments, what is the largest SIMD & OOO system configuration you could run without
10/13/11
Lukasz G. Szafaryn
, …
Jiayuan Meng
18
10/13/11
Caches
Some uncacheable packets for full system simulations are not handled in MV5 caches. Before you switch
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Caches
Some uncacheable packets for full system simulations are not handled in MV5 caches. Before you switch
10/13/11
daniel.tian
10/12/11
How connect MV5sim with terminal
Hi, folks: How can I connect MV5Sim with the terminal? I check the m5term which is included in the M5
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How connect MV5sim with terminal
Hi, folks: How can I connect MV5Sim with the terminal? I check the m5term which is included in the M5
10/12/11