Fwd: Requirements in STMicroelectronics for Greater Noida

[rameez chowdhary]

Dear Students

STMicroelectronics Pvt Ltd have some Urgent Opening, Please see below details.

 

Please send me your resume on mukesh...@gmail.com before 15th March 17.

1.Job Title                 - DFT Expert

   Job Req. No.           - 177940

   Department             - ADG

 

Role Purpose:

 

This team is responsible for the architecture and implementation of advanced DFT/DFD/DFM (design for test/debug/manufacturability) techniques for high performance, highly integrated SoCs. Candidates selected will be directly involved with implementation of various DFT architectures to achieve high quality manufacturing tests that reduce test cost, and increase production quality. In addition, candidates selected will also be involved in all aspects of DFT including architecture, methodology development, design, vector development, manufacturing testing, and debug.

 

Detailed Responsibilities description:

·         Responsible to implement complete design testability cycle from architecture to silicon testing.

·         To ensure adherence to corporate and automotive Testability targets by defining, planning and executing complete flow of DFT, ensuring high coverage, complete Testability, support to failure analysis  and Silicon support to reach Maturity targets.

Skills

Must have skills:

·         Good RTL(VHDL or Verilog or system verilog) writing skills and/or the ability  to  use  industry standard tools like  Tetramax, TestKompress , Design Compiler, etc.

·         Clear concept about scan based design.

·         Knowledge on ATPG and different Fault Models  (SA, Transition, Iddq , SDD etc)

·         Coverage improvement techniques

·         SOC integration and RTL modification as per DFT requirement.

·         Knowledge of Boundary Scan Testing and testing of ips viz ADC, FLASH , PMU in standalone mode

·         Basic knowledge of following :synthesis constraints , ATE ,Silicon defects and its logical effects

·         Awareness of Latest technique viz. Low power ATPG, Analog Bist, Logic Bist would be appreciated and preferred.

Good to have skills:

 

·         Adaptable, Flexible, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.

·         Solutions orientation; Quality driven; Execution minded; Customer focused

 

Work Experience      : 2-5 years

Qualification              : B. Tech/ M.Tech ( Electronics)

            No. of Positions          : 8

 

2.Job Title                  - Sr. DFT Expert

   Job Req. No.           - 177941

   Department             - ADG

 

Role Purpose:

 

This team is responsible for the architecture and implementation of advanced DFT/DFD/DFM (design for test/debug/manufacturability) techniques for high performance, highly integrated SoCs. Candidates selected will be directly involved with implementation of various DFT architectures to achieve high quality manufacturing tests that reduce test cost, and increase production quality. In addition, candidates selected will also be involved in all aspects of DFT including architecture, methodology development, design, vector development, manufacturing testing, and debug.

 

Detailed Responsibilities description:

·         Responsible to implement complete design testability cycle from architecture to silicon testing.

·         To ensure adherence to corporate and automotive Testability targets by defining, planning and executing complete flow of DFT, ensuring high coverage, complete Testability, support to failure analysis  and Silicon support to reach Maturity targets.

Skills

Must have skills:

·         Good RTL(VHDL or Verilog or system verilog) writing skills and/or the ability  to  use  industry standard tools like  Tetramax, TestKompress , Design Compiler, etc.

·         Clear concept about scan based design.

·         Knowledge on ATPG and different Fault Models  (SA, Transition, Iddq , SDD etc)

·         Coverage improvement techniques

·         SOC integration and RTL modification as per DFT requirement.

·         Knowledge of Boundary Scan Testing and testing of ips viz ADC, FLASH , PMU in standalone mode

·         Basic knowledge of following :synthesis constraints , ATE ,Silicon defects and its logical effects

·         Awareness of Latest technique viz. Lowpower ATPG, Analog Bist, Logic Bist would be appreciated and preferred.

Good to have skills:

 

·         Adaptable, Flexible, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.

·         Solutions orientation; Quality driven; Execution minded; Customer focused

 

Work Experience      : 5-7 years

Qualification              : B. Tech/ M.Tech ( Electronics)

            No. of Positions          : 1

 

 

3.Job Title                  - Verification Engineer

   Job Req. No.           - 177963

   Department             - ADG

 

Role Purpose:

 

 The incumbent will be responsible for the Verification and Validation of Digital IP & sub systems. This includes understanding the specifications, proposing an exhaustive & regressive verification environment

 

Detailed Responsibilities description:

 

Responsibilities include

·         Complete Design Verification of digital modules/IPs developed for highly complex SoCs/ASICs to address automotive application.

·         SoC Verification (specs. understanding and micro-architecture definition, RTL coding,) targeted towards Automotive applications

Skills

Must have skills:

 

·         Sound Verilog HDL RTL knowledge and working knowhow of RTL simulations

·         Plan, develop, debug Testbench and Verification Suite at IP module and SoC level.

·         RTL (Verilog/VHDL/system verilog) coding.

·         Sound knowhow of System Verilog for testbench with exposure to verification methodologies like UVM, VMM etc.

·         Assertion based verification or working experience on formal verification (IFV, Jasper)

·         Technical troubleshooting, debugging and demonstrated problem solving skills 

·         RTL code quality and rule checks using spyglass will be desirable.

·         Exposure to gate level simulation and debugging skills.

·         Experience on any of the defect management tools

 

Good to have skills:

 

·         Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.

·         Solutions orientation; Quality driven; Execution minded; Customer focused

 

Work Experience      : 2-5 years

Qualification              : B. Tech/B.E/ M.Tech/ M.E/MSc ( Electronics)

            No. of Positions          : 5

 

 

4.Job Title                  - Sr. Verification Engineer / Team Lead

   Job Req. No.           - 177964

   Department             - ADG

 

Role Purpose:

.

 The incumbent will be responsible for the Verification and Validation of Digital IP & sub systems. This includes understanding the specifications, proposing an exhaustive & regressive verification environment

 

Detailed Responsibilities description:

 

Responsibilities include

·         Complete Design Verification of digital modules/IPs developed for highly complex SoCs/ASICs to address automotive application.

·         SoC Verification (specs. understanding and micro-architecture definition, RTL coding,) targeted towards Automotive applications

Skills

Must have skills:

 

·         Sound Verilog HDL RTL knowledge and working knowhow of RTL simulations

·         Plan, develop, debug Testbench and Verification Suite at IP module and SoC level.

·         RTL (Verilog/VHDL/system verilog) coding.

·         Sound knowhow of System Verilog for testbench with exposure to verification methodologies like UVM, VMM etc.

·         Assertion based verification or working experience on formal verification (IFV, Jasper)

·         Technical troubleshooting, debugging and demonstrated problem solving skills 

·         RTL code quality and rule checks using spyglass will be desirable.

·         Exposure to gate level simulation and debugging skills.

·         Experience on any of the defect management tools

 

Good to have skills:

 

·         Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.

·         Solutions orientation; Quality driven; Execution minded; Customer focused

 

Work Experience      : 6 to 8 years

Qualification              : B. Tech/B.E/ M.Tech/ M.E/MSc ( Electronics)

No. of Positions          : 4

 

For the Team Lead

Work Experience      : 10 plus years

Qualification              : B. Tech/B.E/ M.Tech/ M.E/MSc ( Electronics)

No. of Positions          : 1

 

 

5.Job Title                  - RTL Design

   Job Req. No.           - 177930

   Department             - ADG

 

Role Purpose:

 

SoC and Digital IP Design Development

 

 

Detailed Responsibilities description:

 

Responsibilities include the following for high complexity ASICs targeted for Automotive applications:

·         Complete Digital IP Design flow (specifications and micro-architecture definition, RTL coding and checks (CDC, LINT, logic equivalence)

·         IP integration and SoC assembly using state-of-the-art automated SoC development flow

·         Support to IP/SOC Verification, Validation and Applications teams and ST customers

Skills

Must have skills:

 

·         Digital micro-architecture definition & design partitioning

·         Precise and concise documentation skills

·         RTL (Verilog/VHDL) coding

·         RTL code quality and rule checks

·         Exposure to verification closure

·         Ability to coordinate with implementation teams on synthesis, STA and ECO closure

·         Technical troubleshooting and demonstrated problem solving skills 

·         .

Good to have skills:

 

·         Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.

·         Solutions orientation; Quality driven; Execution minded; Customer focused

 

           Work Experience         : 3-5 years

Qualification                 : B.Tech/BE/M.Tech/ME/MSc (Electronics)

No. of Positions            : 3

 

6.Job Title                  - Backend Design / Senior Backend Design

   Job Req. No.           - 177945

   Department             - ADG

 

Role Purpose:

 

The  incumbent will be involved in design Implementation (Netlist2GDSII flow) of products related to  Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for futuristic cars from the stable of leading car manufacturers ( Eg-Daimler,-Benz, BMW, VOLVO)

 

Detailed Responsibilities description:

 

·         Involved in all aspects of Chip and IP implementation from RTL to GDS - including DC Synthesis, Floor planning and Power Planning and Analysis, Place & Route, Timing closure, Physical Verification, Formal verification and Power analysis.

·          Apart from the obvious challenge of reducing Area, mask re spin, consumption and increasing performance, other challenges include complying to ASIL-D safety standard, striving for zero PPM, crypto subsystem leveraging e-Flash etc.

Skills

Must have skills:

 

·         Knowledge of full RTL to GDSII flow ( Synthesis, STA, Floorplan, CTS, PnR, DRC/LVS, SI, IR Drop )

·         Hands-on experience with Synopsys and Cadence PnR tools, Floorplanning, IR Drop and Physical verification

·         Should have good understanding of Verilog/VHDL

·         Exposure to low power techniques

·         Knowledge of Tcl and Perl scripting is a must

 

Good to have skills:

·         Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.

·         Solutions orientation; Quality driven; Execution minded; Customer focused

 

 

Work Experience      : 2-6 years

Qualification              : B.Tech/BE/M.Tech/ME/MSc (Electronics)

No. of Positions          : 12

 

7.Job Title                  - Backend Design Lead

   Job Req. No.           - 177946

   Department             - ADG

 

Role Purpose:

 

 The  incumbent will be involved in design Implementation (Netlist2GDSII flow) of products related to  Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for futuristic cars from the stable of leading car manufacturers ( Eg-Daimler,-Benz, BMW, VOLVO)

 

Detailed Responsibilities description:

 

·         Involved in all aspects of Chip and IP implementation from RTL to GDS - including DC Synthesis, Floor planning and Power Planning and Analysis, Place & Route, Timing closure, Physical Verification, Formal verification and Power analysis.

·          Apart from the obvious challenge of reducing Area, mask re spin, consumption and increasing performance, other challenges include complying to ASIL-D safety standard, striving for zero PPM, crypto subsystem leveraging e-Flash etc.

Skills

Must have skills:

 

·         Knowledge of full RTL to GDSII flow ( Synthesis, STA, Floorplan, CTS, PnR, DRC/LVS, SI, IR Drop )

·         Hands-on experience with synopsys and Cadence PnR tools, Floorplanning, IR Drop and Physical verification

·         Should have good understanding of verilog/VHDL

·         Exposure to low power techniques

·         Knowledge of Tcl and Perl scripting is a must

.

Good to have skills:

 

·         Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.

·         Solutions orientation; Quality driven; Execution minded; Customer focused

 

 

Work Experience        : 8 to 10 years

Qualification                : B.Tech/BE/M.Tech/ME/MSc (Electronics)

No. of Positions           : 1

 

 

8.Job Title                  - Synthesis

   Job Req. No.           - 177965

   Department             - ADG

 

Role Purpose:

 

The  incumbent will be involved in Synthesis and Timing closure of products related to  Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for futuristic cars from the stable of leading car manufacturers ( Eg-Daimler,-Benz, BMW, VOLVO)

 

Detailed Responsibilities description:

 

·         Involved in the challenge of reducing Area, mask re spin, consumption and increasing performance, other challenges include complying to ASIL-D safety standard, striving for zero PPM, crypto subsystem leveraging e-Flash etc

Skills

Must have skills:

 

·         . Expert in developing chip constraints working with RTL and DFT teams

·         Synthesis and STA Expertise  with Synopsys/Cadence tools

·         Knowledge of full RTL to GDSII flow to take timing closure from RTL to signoff

·         Should have good understanding of Verilog/VHDL

·         Exposure to low power techniques

·         Knowledge of Tcl and Perl scripting is a must

 

Good to have skills:

 

·         Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.

·         Solutions orientation; Quality driven; Execution minded; Customer focused

 

Work Experience      : 2-4 years

Qualification              : B.Tech/BE/M.Tech/ME/MSc (Electronics)

No. of Positions          : 3

 

 

9.Job Title                  - Sr. Synthesis /Team lead

   Job Req. No.           - 177966

   Department             - ADG

 

Role Purpose:

 

The  incumbent will be involved in Synthesis and Timing closure of products related to  Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for futuristic cars from the stable of leading car manufacturers ( Eg-Daimler,-Benz, BMW, VOLVO)

 

Detailed Responsibilities description:

 

·         Involved in the challenge of reducing Area, mask re spin, consumption and increasing performance, other challenges include complying to ASIL-D safety standard, striving for zero PPM, crypto subsystem leveraging e-Flash etc

 

Skills

Must have skills:

 

·         Expert in developing chip constraints working with RTL and DFT teams

·         Synthesis and STA Expertise  with Synopsys/Cadence tools

·         Knowledge of full RTL to GDSII flow to take timing closure from RTL to signoff

·         Should have good understanding of Verilog/VHDL

·         Exposure to low power techniques

·         Knowledge of Tcl and Perl scripting is a must

 

Good to have skills:

 

·         Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.

·         Solutions orientation; Quality driven; Execution minded; Customer focused

 

Work Experience      : 5-7 years

Qualification              : B.Tech/BE/M.Tech/ME/MSc (Electronics)

No. of Positions          : 3

 

 

With Best Regards,

Mukesh

--

With Warm Regards,

RAMEEZ RAJA CHOWDHARY
Lecturer,
School of Electronics (UTD)
Devi Ahilya University (A NAAC Accredited 'A' Grade University),

Khandwa Road, Indore-452001, [M.P.]- India

Mob.No. +91 9617757861