Fwd: VLSI CAD Engineer with Analog Devices India (Bangalore)

[Dp Hussainaiah]

Dear All,

Please check Below job details and apply it if it is suitable to your profile

With Regards,

D.P.Hussain

---------- Forwarded message ----------
From: Niche Search Services <in...@monsterindia.com>
Date: Tue, Jul 9, 2013 at 2:28 PM
Subject: VLSI CAD Engineer with Analog Devices India (Bangalore)
To: dphuss...@gmail.com

To respond back directly to the Employer, please click on Reply button, or send an email to res...@nichesearch.net (Please don't delete or modify while replying to this email) For Internal Use of Employer - Monster Resume ID: 31503075      Personal Folder ID: 13301954

Dear Dudekula Pedda, Hi, We are an executive search firm based in Bangalore.At present we have an opportunity with Analog Devices India (Bangalore).The requirement details are given below If this position interests you pls mail me your mail your profile along with the following details Present CTC Expected salary Notice Period Note: Candidates experienced into PHYSICAL DESIGN only apply. Others please ignore. -- Thanks & Regards Archana Niche Search Services, Bangalore Job Description: Work on a team of CAD engineers responsible for development and application of CAD software engineering methods, theories and applied research techniques for IC product development at India, Bangalore. The team is part of corporate CAD team that is based in ADI, Bangalore. · Responsible for CAD methodology development and deployment in back-end Digital design implementation domain. It includes chip floor-planning, design placement, signal/power routing, chip finishing and design sign-off. · Responsible for automating, maintaining and supporting internal reference digital design implementation methodology. · Responsible for CAD/EDA software evaluation and qualification of industry standard CAD tools in back-end design implementation domain. · Need to develop EDA software QA/acceptance test plan, test structures and automate qualification of CAD tools for general release within the company. · Experience in using industry standard EDA tools for chip floor-planning, design placement, signal/power routing, chip finishing and design sign-off for designs in nanometer technology process nodes is required. Synopsys IC-Compiler, Cadence Encounter Digital Implementation, Synopsys PrimeTime-SI/PX and Cadence EPS tool experience is preferred. Qualification/Experience: · Bachelor of Engineering degree with 3-4 years and Masters with 1-2 years in Electrical / Electronics & Comm discipline with min. 65% only apply. · Ability to write PERL/SHELL/TCL scripts and small software programs · Must possess excellent communication skills both oral and written

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