Re: Instruction scheduling and selection in IonMonkey

[Ting-Yuan Huang]

Here is another stop-sign:

M. G. Valluri and R. Govindarajan. 1999. Evaluating register allocation and instruction scheduling techniques in out-of-order issue processors. In Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques. Washington, DC: IEEE Computer Society Press.

The experiments showed that the traditional schedulers made insignificant effects an ooo processor. However, a scheduler that targeted at minimizing register pressure helped marginally:

R. Govindarajan, H. Yang, C. Zhang, J. Nelson Amaral, and G. R. Gao. 2001. Minimum register instruction sequence problem: Revisiting optimal code generation for dags. In Proceedings of the International Parallel and Distributed Processing Symposium.


----- Original Message -----
From: "Ting-Yuan Huang" <thu...@mozilla.com>
To: "Jeff Walden" <jwald...@mit.edu>
Cc: dev-tech-js-en...@lists.mozilla.org
Sent: Monday, March 18, 2013 4:26:23 PM
Subject: Re: [JS-internals] Instruction scheduling and selection in IonMonkey


Thanks for the explanation! Sounds like that those dynamic techniques (out of order execution, register renaming, etc.) dominated the static scheduler in compiler, especially on beasts like x86.

AFAIK, ARM introduced ooo and register renaming to cortex-a9, but I've no idea how effective it is. I can do some experiments on various ARM CPUs if needed.

BTW, could you please suggest some low-hanging fruit? :-) Before this thread I used to think of an instruction scheduler a big fruit.

----- Original Message -----
From: "Jeff Walden" <jwald...@mit.edu>
To: dev-tech-js-en...@lists.mozilla.org
Sent: Monday, March 18, 2013 7:55:08 AM
Subject: Re: [JS-internals] Instruction scheduling and selection in IonMonkey

On 03/15/2013 09:17 AM, Andreas Gal wrote:
> We did some research work on this for JIT compilers way back at UCI as part of my thesis. This was 5 years ago and the architecture world was different, and this was focused on x86, but the rough result was that on x86 all that matters is scheduling division and memory access. The rest was irrelevant. The hardware can see much further ahead in the dynamic instruction stream than you can easily do in software, especially when compiling under time pressure (its a JIT!).

This basically matches my knowledge from a compiler class I took around the same time. Someone took the test programs we were to compile and did a ton of hand-scheduling of things (to decide which optimizations we should implement in the limited time we had) and found it didn't make any difference at all to ultimate speed.

I don't know anything about ARM capabilities now, but to the extent ARM chips aren't as smart, I'd want to know what the chances are that newer ARM chips will be smarter in this regard, before spending a lot of time on instruction scheduling. There seems to be a lot of other low-hanging fruit we should pick first, even if it were valuable on ARM.

Jeff
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