Xilinx CoreGen Issue (vcom-13)

[aquar...@gmail.com]

All,
I've been chasing an error for the last few days and, having found
help primarily on non-English language websites (Google Translator
ftw), I thought I'd post it here for posterity.
After downloading the lastest xilinxcorelib files, I started getting
vcom-13 errors, that is "Error: (vcom-13) Recompile work.mymod because
ieee.std_logic_1164 has changed." Clearly I was unable to do so as I
received these as precompiled files from Xilinx. A few attempts at
monkeying around with my ModelSim DO file led to numerous other
errors, including vsim-3173 (Entity 'work.mymod' has no
architecture.), but finally I stumbled across the -force_refresh
instruction.
Executing "vcom -force_refresh -work xilinxcorelib" solved my
problems.
I hope this helps someone,
Aqua