** Error: mux1_sim.vhd(14): near ")": (vcom-1576) expecting IDENTIFIER.

[Cherry]

How do i resolve the error in the following code?

** Error:   mux1_sim.vhd(14): near ")": (vcom-1576) expecting IDENTIFIER.

library IEEE;

use IEEE.std_logic_1164.all;

--use work.std_arith.all;

use IEEE.numeric_std;

entity mux1_sim is

port (

  signal1: in std_logic;

 signal1_red: in std_logic;

   data_mux1: in std_logic;

      mux1_sel: out std_logic;

  mux1_wr: out std_logic;

   MRST: out std_logic; 

);

end mux1_sim;

  

architecture Behaviour71 of mux1_sim is

signal S0, S1, D;

signal RS_b, WR_b

begin 

rss <=( ext_rstn='1');

C1: process(mux1_sel)

RS_b<=MRST;

WR_b<=mux1_wr;

S0<=signal1;

S1<=signal1_red;

begin

if(RS_b=1)then

if(WR_b='1' and WR_b'event)then 

D=D;

elseif(WR_b='0')

if(mux1_sel='0')

D=S0;

else

D= S1

            end if;

end if;

else

D=0;

end if;

end process;

data_mux1<=D;

end Behaviour71;

[Dorin Dragan]

The last port in the port list should not be followed by a semicolon (;)

--
You received this message because you are subscribed to the Google Groups "ModelSim PE Student Edition" group.
To unsubscribe from this group and stop receiving emails from it, send an email to modelsim-pe-student...@googlegroups.com.
To post to this group, send email to modelsim-pe-s...@googlegroups.com.
Visit this group at http://groups.google.com/group/modelsim-pe-student-edition.
For more options, visit https://groups.google.com/d/optout.

[Cherry]

Thank You Dorin, 

That helped. 

To unsubscribe from this group and stop receiving emails from it, send an email to modelsim-pe-student-edition+unsub...@googlegroups.com.

[Vivin Arikkudil]

Hello guys,

Can some one help me with the following error. Please don't criticize as i am only beginning to learn FPGA.

 Error: C:/Modeltech_pe_edu_10.4a/examples/LEDm.vhd(19): near "process": (vcom-1576) expecting BEGIN.

library ieee;

use ieee.std_logic_1164.all;

entity LEDm is

port(

enb:in std_logic;

clk:in std_logic;

pre:in std_logic;

rst:in std_logic;

f:out std_logic;

a:out std_logic;

b:out std_logic;

g:out std_logic

);

end LEDm;

architecture rtl of LEDm is

begin 

 process (clk,rst)

  begin

if rising_edge(clk) then

f<=(not f and not b)or(not f and a and g)or( not f and not a and not g);

a<=(not f and not b and not g) or ( not f and not a and not b);

b<=(not f and not a and not b) or ( not f and a and not b and not g);

g<=(not f and a) or (not f and b and g);

 

elsif rst then 

f<='1';

a<='0';

b<='0';

g<='0';

end if;

 end process;

end rtl;