Work library is empty after compiling Verilog source file in Modelsim

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AmirHossien Shahpoori

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Apr 16, 2021, 1:16:05 PM4/16/21
to ModelSim PE Student Edition
Hi

I have a problem to simulate. After I compiled my file , Work Library is Empty 

How can I solve this problem?


Screenshot 2021-04-16 213138.jpg

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