Bug Report - SystemVerilog generated modports broken after 'restart' command
Edmond Coté
I have been testing out generatable modports and modport expressions
in SystemVerilog, the bug I found is described below. As an academic
user, I could place a formal request to submit a bug report directly
to Mentor, however, I have done this in the past for another product,
and it is not worth the effort. The bug was reproduced on the latest
student edition, not on my production "academic" machine that is
running 6.2.
Please contact me for further information, and to update me on the
status of this request
Thank you
-- Edmond Coté
----------------------------------------
interface request_bus_if;
generate
genvar i;
// Master
for (i=0; i<NUM_MASTER; i++) begin : mmp
modport master_mp
(
output .address(address[i]),
output .command(command[i]),
output .tag(tag[i]),
output .valid(valid[i]),
);
end
[...]
endinterface // request_bus_if
----------------------------------------
Instantiate module with request bus (abbreviated),
[...]
request_bus_if #(.NUM_MASTER(2), .NUM_SLAVE(1)) request_bus(clock,
reset);
cache_controller cache_ctrlr_0 (clock, reset,
request_bus.mmp[0].master_mp);
[...]
----------------------------------------
Please note how the system does not simulate, or elaboration fails,
after the 'restart' command is issued. Simulation must be restarted.
$ vsim -c system_tb
[...]
VSIM 1> run 1 us
run 1 us
VSIM 2> restart -f
# ** Fatal: (vsim-3695) hdl/system.v(49): The interface port
'request_bus' must be passed an actual interface.
# Time: 0 ns Iteration: 0 Instance: /system_tb/dut/cache_ctrlr_0
File: hdl/processor/cache_controller.v
VSIM 3> vsim -c system_tb
[...]
VSIM 4> run 1 us
run 1 us
Edmond Coté
cache_ctrlr_0 in a generate block. Recall that when the module was
instantiated without a generate block, the simulation could NOT be
restarted. Running, and restarting, the simulation now works as
intended.
Feel free to send me a free tee-shirt, or heck, make me a job offer
(I'll done with grad school in a matter of weeks) :P. Of course, I'm
kidding (or am I?), but all that I really ask if that someone forwards
this bug report to those in charge of the Verilog/SystemVerilog front-
end.
Thank you,
-- Edmond Coté
e.g.
generate
genvar i;
for (i=0; i<1; i++) begin : master_device
cache_controller cache_ctrlr(clock, reset,
request_bus.mmp[i].master_mp);
end
endgenerate
