Simulation of IP Core

[spp...@gmail.com]

I am using Xilinx-ISE 9.1 WabPack and for simulation ModelSim PE
Student Edition 6.3C.
In my design I am using Dual port Block RAM IP core. When ever I did
the behavioral simulation , ModelSim gives error "PE Student Edition
supports only a single HDL
# Error loading design"

It would be great If any one give me the solution for this problem .

Thanks

[Mike Aitken]

Am I correct in saying that ModelSIM PE Student Edition only supports
using one type of HDL (i.e. Verilog OR VHDL, but not both) ??