Seminário de Arquitetura
Rodolfo Azevedo
Hardware specialization, in the form of accelerators that provide custom datapath and control for specific algorithms and applications, promises impressive performance and en- ergy advantages compared to traditional architectures. Cur- rent research in accelerator analysis relies on RTL-based synthesis flows to produce accurate timing, power, and area es- timates. Such techniques not only require significant effort and expertise but are also slow and tedious to use, making large design space exploration infeasible. To overcome this problem, we present Aladdin, a pre-RTL, power-performance acceler- ator modeling framework and demonstrate its application to system-on-chip (SoC) simulation. Aladdin estimates perfor- mance, power, and area of accelerators within 0.9%, 4.9%, and 6.6% with respect to RTL implementations. Integrated with architecture-level core and memory hierarchy simulators, Aladdin provides researchers an approach to model the power and performance of accelerators in an SoC environment.