Seminário de Arquitetura - Segunda 10:00 - Sala 361
Rodolfo Azevedo
Resumo: Most multi-core architectures nowadays support dynamic volt- age and frequency scaling (DVFS) to adapt their speed to the system’s load and save energy. Some recent architectures addi- tionally allow cores to operate at boosted speeds exceeding the nominal base frequency but within their thermal design power.
In this paper, we propose a general-purpose library that allows selective control of DVFS from user space to accelerate multi-threaded applications and expose the potential of hetero- geneous frequencies. We analyze the performance and energy trade-offs using different DVFS configuration strategies on sev- eral benchmarks and real-world workloads. With the focus on performance, we compare the latency of traditional strategies that halt or busy-wait on contended locks and show the power implications of boosting of the lock owner. We propose new strategies that assign heterogeneous and possibly boosted fre- quencies while all cores remain fully operational. This allows us to leverage performance gains at the application level while all threads continuously execute at different speeds. We also derive a model to help developers decide on the optimal DVFS configuration strategy, e.g, for lock implementations. Our in- depth analysis and experimental evaluation of current hardware provides insightful guidelines for the design of future hardware power management and its operating system interface.