Google Groups no longer supports new Usenet posts or subscriptions. Historical content remains viewable.
Dismiss
Architecture specific code for tickless kernel
17 views
Skip to first unread message
neo
Apr 19, 2011, 1:07:41 PM4/19/11
to
Hi,
I am developing a BSP for a ARM Cortex-M3 (no MMU) based board. In
order to have tickless kernel and deferrable timers, what are the
architecture specific implementations. Can some one point out some
examples that already have this feature enabled and also in the kernel
tree.
I am developing a BSP for a ARM Cortex-M3 (no MMU) based board. In
order to have tickless kernel and deferrable timers, what are the
architecture specific implementations. Can some one point out some
examples that already have this feature enabled and also in the kernel
tree.
And also, are clocksoure and clockevents dependent on each other? I
see in some platforms, that they have used 2 different timers for the
above. If it can be used so, which ties up the clocksource and
clockevent?
Thanks in advance
neo
0 new messages