A potential solution for stability issues on the Ci20 V1 purple

[Gabriele Svelto]

Hi all,
like many others in this list I've experienced stability issues on my
Creator CI20. All evidence pointed to a memory issue (random freezes,
segfaults, kernel crashes; etc...) so I finally found some time to dig
into it. What I discovered is that the DDR timings set by U-boot for my
board contained some errors. I have a V1 purple board with Samsung
K4B2G0846Q DDR3 chips. Looking at the datasheet [1] for those chips I
noticed that the value for tFAW was 40 clocks while the ImgTec fork of
U-boot used 30 cycles instead. Additionally the definition for tXP was
identical to the H5TQ2G83CFR chips, but then a different value was used
in the timing register. After these changes I managed to run a 12 hours
long compilation on my board w/o crashes or other issues, something I
never managed to pull off before. I can't be sure this fixes all the
problems as I had to guess what should end up in the timing registers
but it seems to have been good enough for me. You can find the U-boot
sources with the adjusted values at [2].

If anybody has some documentation on the memory controller it would be
appreciated as that would allow me to verify all the other timings too.

Gabriele

[1] https://www.setphaserstostun.org/ci20/K4B2G0846Q-Samsung.pdf
[2] https://github.com/gabrielesvelto/CI20_u-boot/tree/fixed-timings

[Maarten ter Huurne]

On Wednesday, 25 July 2018 14:23:17 CEST Gabriele Svelto wrote:

> If anybody has some documentation on the memory controller it would be
> appreciated as that would allow me to verify all the other timings
> too.

The DDR controller is described in chapter 15 of the JZ4780 Programming
Manual.

ftp://ftp.ingenic.com/SOC/JZ4780/JZ4780_pm.pdf

Bye,
Maarten