U-Boot and sdram init

[Kai Nacke]

Hi!

Well, my CI20 was very unstable until I tried the patch from Gabriele Svolto (Thanks for that!). Now it is running much better.

I decided to have another look at it and found something strange.

I have a purple CI20 board with the Samsung K4B2G0846Q chips on it. According to https://elinux.org/CI20_Hardware#DDR.2FRAM it is a Rev B board.

On startup, U-Boot identifies a Rev 1 board. The revision is computed in the ci20_revision() function https://github.com/MIPS/CI20_u-boot/blob/ci20-v2013.10/board/imgtec/ci20/ci20.c#L172 and printed in the checkboard() function. ci20_revision() return 0, 1 or 2 which fits nicely to the documented Rev A, Rev B and V2 labels.

The same function is also used in the sdram_init() function from https://github.com/MIPS/CI20_u-boot/blob/ci20-v2013.10/arch/mips/cpu/xburst/jz4780/sdram.c#L219.

Starting at line 231 is the following code:

board_revision = ci20_revision(); if (board_revision == 2) #ifdef CONFIG_SYS_DDR3_K4B2G0846Q #if CONFIG_SYS_CPU_SPEED == 1200000000 && CONFIG_SYS_EXTAL == 48000000 ddr_config = &K4B2G0846Q_48_config; #else #error No DDR configuration for CPU speed #endif #else #error K4B2G0846Q support disabled #endif else /* Fall back to H5TQ2G83CFR RAM */ #ifdef CONFIG_SYS_DDR3_H5TQ2G83CFR #if CONFIG_SYS_CPU_SPEED == 1200000000 && CONFIG_SYS_EXTAL == 48000000 ddr_config = &H5TQ2G83CFR_48_config; #else #error No DDR configuration for CPU speed #endif #else #error H5TQ2G83CFR support disabled #endif

My interpretation of this piece of code is that the initialization of the Samsung rams is only used for the V2 board, but not for my Rev B board.

Do I make a mistake here or is this really a bug?

Regards,

Kai