[RFC 4/5] ASoC: codecs: adjust jz4780 registers and make code compile

[H. Nikolaus Schaller]

Does not work (some registers are still missing, some FIXMEs noted).

Signed-off-by: H. Nikolaus Schaller <h...@goldelico.com>
---
sound/soc/codecs/jz4780.c | 104 ++++++++++++++++++++++++++------------
1 file changed, 73 insertions(+), 31 deletions(-)

diff --git a/sound/soc/codecs/jz4780.c b/sound/soc/codecs/jz4780.c
index 013bed2a92fa5..39a65b390d027 100644
--- a/sound/soc/codecs/jz4780.c
+++ b/sound/soc/codecs/jz4780.c
@@ -38,46 +38,70 @@

/* Internal register space, accessed through regmap */
enum {
- JZ4780_CODEC_REG_SR,
- JZ4780_CODEC_REG_AICR_DAC,
- JZ4780_CODEC_REG_AICR_ADC,
- JZ4780_CODEC_REG_CR_LO,
- JZ4780_CODEC_REG_CR_HP,
-
- JZ4780_CODEC_REG_MISSING_REG1,
-
- JZ4780_CODEC_REG_CR_DAC,
- JZ4780_CODEC_REG_CR_MIC,
- JZ4780_CODEC_REG_CR_LI,
- JZ4780_CODEC_REG_CR_ADC,
- JZ4780_CODEC_REG_CR_MIX,
- JZ4780_CODEC_REG_CR_VIC,
+/* table follows register definitions of JZ4770_CODEC */
+ JZ4780_CODEC_REG_SR = 0x00,
+ JZ4780_CODEC_REG_SR2 = 0x01,
+ JZ4780_CODEC_REG_MR = 0x07,
+ JZ4780_CODEC_REG_AICR_DAC = 0x08,
+ JZ4780_CODEC_REG_AICR_ADC = 0x09,
+ JZ4780_CODEC_REG_CR_LO = 0x0b,
+ JZ4780_CODEC_REG_CR_HP = 0x0d,
+
+ /* JZ4780_CODEC_REG_MISSING_REG1, */
+
+ JZ4780_CODEC_REG_CR_DAC = 0x17,
+ JZ4780_CODEC_REG_CR_DMIC = 0x10,
+ /* JZ4780_CODEC_REG_CR_MIC, */
+ JZ4780_CODEC_REG_CR_MIC1 = 0x11,
+ JZ4780_CODEC_REG_CR_MIC2 = 0x12,
+JZ4780_CODEC_REG_CR_MIC = JZ4780_CODEC_REG_CR_MIC1, /* FIXME in code... */
+ /* JZ4780_CODEC_REG_CR_LI */
+ JZ4780_CODEC_REG_CR_LI1 = 0x13,
+ JZ4780_CODEC_REG_CR_LI2 = 0x13,
+JZ4780_CODEC_REG_CR_LI = JZ4780_CODEC_REG_CR_LI1, /* FIXME in code... */
+ JZ4780_CODEC_REG_CR_ADC = 0x18,
+ JZ4780_CODEC_REG_CR_MIX = 0x19,
+ JZ4780_CODEC_REG_CR_VIC = 0x1b,
+
+ /* which is this on jz4780? */
+ /*
JZ4780_CODEC_REG_CCR,
JZ4780_CODEC_REG_FCR_DAC,
JZ4780_CODEC_REG_FCR_ADC,
- JZ4780_CODEC_REG_ICR,
- JZ4780_CODEC_REG_IMR,
- JZ4780_CODEC_REG_IFR,
- JZ4780_CODEC_REG_GCR_HPL,
- JZ4780_CODEC_REG_GCR_HPR,
- JZ4780_CODEC_REG_GCR_LIBYL,
- JZ4780_CODEC_REG_GCR_LIBYR,
- JZ4780_CODEC_REG_GCR_DACL,
- JZ4780_CODEC_REG_GCR_DACR,
- JZ4780_CODEC_REG_GCR_MIC1,
- JZ4780_CODEC_REG_GCR_MIC2,
- JZ4780_CODEC_REG_GCR_ADCL,
- JZ4780_CODEC_REG_GCR_ADCR,
-
- JZ4780_CODEC_REG_MISSING_REG2,
-
+ */
+
+ JZ4780_CODEC_REG_ICR = 0x23,
+ JZ4780_CODEC_REG_IMR = 0x24,
+ JZ4780_CODEC_REG_IFR = 0x25,
+ JZ4780_CODEC_REG_GCR_HPL = 0x28,
+ JZ4780_CODEC_REG_GCR_HPR = 0x29,
+ JZ4780_CODEC_REG_GCR_LIBYL = 0x2a,
+ JZ4780_CODEC_REG_GCR_LIBYR = 0x2b,
+ JZ4780_CODEC_REG_GCR_DACL = 0x2c,
+ JZ4780_CODEC_REG_GCR_DACR = 0x2d,
+ JZ4780_CODEC_REG_GCR_MIC1 = 0x2e,
+ JZ4780_CODEC_REG_GCR_MIC2 = 0x2f,
+ JZ4780_CODEC_REG_GCR_ADCL = 0x30,
+ JZ4780_CODEC_REG_GCR_ADCR = 0x31,
+
+ /* JZ4780_CODEC_REG_MISSING_REG2, */
+
+ /* which is this on jz4780? */
+ /*
JZ4780_CODEC_REG_GCR_MIXADC,
JZ4780_CODEC_REG_GCR_MIXDAC,
+ */
+
+ /* AGC0..4 is read/written indirectly through CR_ADC_AGC
+ so we might need another indirect regmap */
JZ4780_CODEC_REG_AGC1,
JZ4780_CODEC_REG_AGC2,
JZ4780_CODEC_REG_AGC3,
JZ4780_CODEC_REG_AGC4,
JZ4780_CODEC_REG_AGC5,
+ */
+
+ JZ4780_CODEC_REG_MAXREG = 0x3b,
};

#define REG_AICR_DAC_ADWL_OFFSET 6
@@ -616,6 +640,8 @@ static void jz4780_codec_codec_init_regs(struct snd_soc_component *codec)
regmap_set_bits(regmap, JZ4780_CODEC_REG_AICR_DAC,
REG_AICR_DAC_SERIAL | REG_AICR_DAC_I2S);

+/* FIXME: handle JACK_EVENT */
+
/* The generated IRQ is a high level */
regmap_clear_bits(regmap, JZ4780_CODEC_REG_ICR, REG_ICR_INT_FORM_MASK);
regmap_update_bits(regmap, JZ4780_CODEC_REG_IMR, REG_IMR_ALL_MASK,
@@ -623,14 +649,18 @@ static void jz4780_codec_codec_init_regs(struct snd_soc_component *codec)
REG_IMR_RDO_MASK | REG_IMR_GUP_MASK |
REG_IMR_GDO_MASK);

+#if FIXME
/* 12M oscillator */
regmap_clear_bits(regmap, JZ4780_CODEC_REG_CCR, REG_CCR_CRYSTAL_MASK);
+#endif

/* 0: 16ohm/220uF, 1: 10kohm/1uF */
regmap_clear_bits(regmap, JZ4780_CODEC_REG_CR_HP, REG_CR_HP_LOAD);

+#if FIXME
/* disable automatic gain */
regmap_clear_bits(regmap, JZ4780_CODEC_REG_AGC1, REG_AGC1_EN);
+#endif

/* Disable DAC lrswap */
regmap_set_bits(regmap, JZ4780_CODEC_REG_CR_DAC, REG_CR_DAC_LRSWAP);
@@ -725,16 +755,20 @@ static int jz4780_codec_hw_params(struct snd_pcm_substream *substream,
regmap_update_bits(codec->regmap, JZ4780_CODEC_REG_AICR_DAC,
REG_AICR_DAC_ADWL_MASK,
bit_width << REG_AICR_DAC_ADWL_OFFSET);
+#if FIXME
regmap_update_bits(codec->regmap, JZ4780_CODEC_REG_FCR_DAC,
REG_FCR_DAC_FREQ_MASK,
rate << REG_FCR_DAC_FREQ_OFFSET);
+#endif
} else {
regmap_update_bits(codec->regmap, JZ4780_CODEC_REG_AICR_ADC,
REG_AICR_ADC_ADWL_MASK,
bit_width << REG_AICR_ADC_ADWL_OFFSET);
+#if FIXME
regmap_update_bits(codec->regmap, JZ4780_CODEC_REG_FCR_ADC,
REG_FCR_ADC_FREQ_MASK,
rate << REG_FCR_ADC_FREQ_OFFSET);
+#endif
}

return 0;
@@ -781,8 +815,10 @@ static bool jz4780_codec_volatile(struct device *dev, unsigned int reg)
static bool jz4780_codec_readable(struct device *dev, unsigned int reg)
{
switch (reg) {
+#if FIXME
case JZ4780_CODEC_REG_MISSING_REG1:
case JZ4780_CODEC_REG_MISSING_REG2:
+#endif
return false;
default:
return true;
@@ -793,8 +829,10 @@ static bool jz4780_codec_writeable(struct device *dev, unsigned int reg)
{
switch (reg) {
case JZ4780_CODEC_REG_SR:
+#if FIXME
case JZ4780_CODEC_REG_MISSING_REG1:
case JZ4780_CODEC_REG_MISSING_REG2:
+#endif
return false;
default:
return true;
@@ -819,6 +857,7 @@ static int jz4780_codec_reg_read(void *context, unsigned int reg,
int ret;

ret = jz4780_codec_io_wait(codec);
+
if (ret)
return ret;

@@ -842,6 +881,7 @@ static int jz4780_codec_reg_write(void *context, unsigned int reg,
int ret;

ret = jz4780_codec_io_wait(codec);
+
if (ret)
return ret;

@@ -849,6 +889,7 @@ static int jz4780_codec_reg_write(void *context, unsigned int reg,
codec->base + ICDC_RGADW_OFFSET);

ret = jz4780_codec_io_wait(codec);
+
if (ret)
return ret;

@@ -867,7 +908,7 @@ static struct regmap_config jz4780_codec_regmap_config = {
.reg_bits = 7,
.val_bits = 8,

- .max_register = JZ4780_CODEC_REG_AGC5,
+ .max_register = JZ4780_CODEC_REG_MAXREG,
.volatile_reg = jz4780_codec_volatile,
.readable_reg = jz4780_codec_readable,
.writeable_reg = jz4780_codec_writeable,
@@ -901,6 +942,7 @@ static int jz4780_codec_probe(struct platform_device *pdev)

codec->regmap = devm_regmap_init(dev, NULL, codec,
&jz4780_codec_regmap_config);
+
if (IS_ERR(codec->regmap))
return PTR_ERR(codec->regmap);

--
2.26.2