[PATCH 04/13] MIPS: Ingenic: Fix the wrong cpu features.

[周琰杰 (Zhou Yanjie)]

1.Ingenic SoCs have never had a instruction cache with virtual tag,
so the "cpu_has_vtag_icache" in cpu-feature-overrides.h should be
0, and the flag in cpu-probe.c should also be removed.
2.Ingenic XBurst®1 CPU does not implement the UserLocal register but
XBurst®2 CPU does, so remove the "#define cpu_has_userlocal 0" and
detect whether the processor supports UserLocal register through
"cpu_probe_ingenic()".

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouy...@wanyeetech.com>
---
arch/mips/include/asm/mach-ingenic/cpu-feature-overrides.h | 3 +--
arch/mips/kernel/cpu-probe.c | 3 ---
2 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/arch/mips/include/asm/mach-ingenic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ingenic/cpu-feature-overrides.h
index 7c5e576..8e8d363 100644
--- a/arch/mips/include/asm/mach-ingenic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ingenic/cpu-feature-overrides.h
@@ -28,7 +28,7 @@
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
#define kernel_uses_llsc 1
-#define cpu_has_vtag_icache 1
+#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_pindexed_dcache 0
@@ -38,7 +38,6 @@
#define cpu_has_dsp 0
#define cpu_has_dsp2 0
#define cpu_has_mipsmt 0
-#define cpu_has_userlocal 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index e685369..049d04d 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1805,9 +1805,6 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
c->options &= ~MIPS_CPU_COUNTER;
BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter);

- /* XBurst has virtually tagged icache */
- c->icache.flags |= MIPS_CACHE_VTAG;
-
switch (c->processor_id & PRID_IMP_MASK) {

/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
--
2.7.4