Spartan 3AN (2)

Ulrich Staudinger

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May 26, 2012, 3:46:34 PM5/26/12

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Hi there,

as a followup to my former spartan 3 an inquiry ... I have started a wiki page on my site to document the procedure and process:

http://developers.activequant.org/projects/aq-fix-fpga/wiki/Compiling_minsoc_for_spartan_3an

in my platform specific minsoc_defines.v, I defined:

`define SPARTAN3AN

at the moment, ngdbuild fails.

I see lot's of :


WARNING:Xst:916 - "/home/ustaudinger/minsoc/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v" line 225: Delay is ignored for synthesis.
WARNING:Xst:916 - "/home/ustaudinger/minsoc/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v" line 227: Delay is ignored for synthesis.
WARNING:Xst:916 - "/home/ustaudinger/minsoc/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v" line 239: Delay is ignored for synthesis.
WARNING:Xst:916 - "/home/ustaudinger/minsoc/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v" line 241: Delay is ignored for synthesis.
WARNING:Xst:916 - "/home/ustaudinger/minsoc/minsoc/prj/../rtl/verilog/or1200/rtl/verilog/or1200_iwb_biu.v" line 245: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Mo

from xst ....

and later on :

ERROR:NgdBuild:604 - logical block 'tap_top' with type

'minsoc_xilinx_internal_jtag' could not be resolved. A pin name misspelling

can cause this, a missing edif or ngc file, case mismatch between the block

name and the edif or ngc file name, or the misspelling of a type name. Symbol

'minsoc_xilinx_internal_jtag' is not supported in target 'spartan3a'.

ERROR:NgdBuild:604 - logical block 'onchip_ram_top/MEM[3].block_ram_3' with type

'minsoc_onchip_ram' could not be resolved. A pin name misspelling can cause

this, a missing edif or ngc file, case mismatch between the block name and

the edif or ngc file name, or the misspelling of a type name. Symbol

'minsoc_onchip_ram' is not supported in target 'spartan3a'.

...

I have no clue where "spartan3a" comes from. I did even a grep through the entire MINSOC folder and couldn't find a reference.

Nonetheless, I see ifdefs about SPARTAN3A all over the place. So I guess, simply defining SPARTAN3AN is not the right solution.

When I define in my spartan3an backend folder, the system name as SPARTAN3A, then "make all" proceeds smooth down to bit map gen, but prints out a final warning:

Creating bit map...

WARNING:Bitgen:242 - CLKIN_PERIOD is set to 0 ps which is less than the minimum

of 3067 ps. The CLKIN_PERIOD is the period of the input clock to the DCM. The

CLKIN_PERIOD is used by the DCM for frequency synthesis. To set the

CLKIN_PERIOD in the UCF use the syntax: INST "DCM instance name"

CLKIN_PERIOD=X ns;

Saving bit stream in "minsoc.bit".

Bitstream generation is complete.

bitgen then complains:

...

WARNING:PhysDesignRules:812 - Dangling pin <DOB31> on

block:<or1200_top/or1200_cpu/or1200_rf/rf_b/ramb16_s36_s36>:<RAMB16BWE_RAMB16

BWE>.

ERROR:PhysDesignRules:10 - The network <or1200_top/or1200_du/dcr5<6>> is

completely unrouted.

....

and stops.

Any help, possibly also pointers to other forums or mailing list appreciated ...

thanks

ulrich

--

Ulrich Staudinger

http://www.activequant.com
Connect online: https://www.xing.com/profile/Ulrich_Staudinger

Raul Fajardo

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May 27, 2012, 3:56:24 AM5/27/12

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Hi Ulrich,

Im currently abroad with restricted internet access. Spartan3an is simply a spartan3a with non volatile configuration if my memory doesnt fail on me. Basically, you would have to use spartan3a on minsoc_defines but define some your part as 3an on the configure script.

Id like to help you more. But i cant check more things at the moment. Hopefully, you will find out or someone will ve able to help you.

I didnt understand what went wrong on your bitgen. It first seems that it worked. Then, your pasted errors give hint that the rtl code from or1200 would be incomplete. That could arise from reductions related to other missing implementations due to the spartan3an definition. Try make clean and make all again because the system might have tried to work with codes from two different implementations by mistake.

I wish you good luck,
Raul

Ulrich Staudinger

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May 27, 2012, 9:23:13 AM5/27/12

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Hi Raul,

I am so glad that you responded.

So, to recap, I will try the following:

1) Use 'define SPARTAN3A in my spartan3an_starter_kit folder

2) Modify the constraints file (.ucf) to use the references as defined for my spartan3an kit. - some resources are named differently between spartan3a and spartan3an

3) run configure again in the backend folder

5) make distclean in the syn folder

6) make all in the syn folder

7) try bitgen then promgen then impact once more.

I'll let you know the result.

By the way, if all this works, I think I should add at least some little wishbone slave or some GPIO slave or something that just blinks one of those LEDs, so that I see that my box works. The RS232/UART part is still a bit obscure to me (too many external parts, too many parameters, etc).

Talk to you later,

Ulrich

Ulrich Staudinger

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May 27, 2012, 10:12:18 AM5/27/12

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Well ... one step further.

So, I used spartan3a_dsp_kit as a start. I recreated the .ucf file, set the device part in configure from

DEVICE_PART='xc3sd1800a-4-fg676'

to

DEVICE_PART='xc3s700an-4-fgg484'

and reran syn/make all

This yielded:

map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd
Release 13.4 - Map O.87xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Using target part "3s700anfgg484-4".
WARNING:Map:306 - The -retiming options can't be used for the targeted device
family. Map will run and ignore the -retiming option.
WARNING:Map:228 - The command line option -equivalent_register_removal can only
be used when running in global optimization mode (-global_opt). The option
will be ignored.
Mapping design into LUTs...
Writing file minsoc.ngm...
Running directed packing...
WARNING:Pack:266 - The function generator
or1200_top/or1200_cpu/or1200_alu/Sh26960 failed to merge with F5 multiplexer
or1200_top/or1200_cpu/or1200_alu/result<13>135_f5. There is a conflict for
the FXMUX. The design will exhibit suboptimal timing.
Running delay-based LUT packing...
Updating timing models...
ERROR:Pack:2310 - Too many comps of type "RAMB16BWE" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device. Please check the
Design Summary section to see which resource requirement for your design
exceeds the resources available in the device. Note that the number of slices
reported may not be reflected accurately as their packing might not have been
completed.

... so I changed in minsoc_defines.v, the memory width from 15 to 12.

This yielded:

map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd
Release 13.4 - Map O.87xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Using target part "3s700anfgg484-4".
WARNING:Map:306 - The -retiming options can't be used for the targeted device
family. Map will run and ignore the -retiming option.
WARNING:Map:228 - The command line option -equivalent_register_removal can only
be used when running in global optimization mode (-global_opt). The option
will be ignored.
Mapping design into LUTs...
Writing file minsoc.ngm...
Running directed packing...
WARNING:Pack:266 - The function generator
or1200_top/or1200_cpu/or1200_alu/Sh26960 failed to merge with F5 multiplexer
or1200_top/or1200_cpu/or1200_alu/result<13>135_f5. There is a conflict for
the FXMUX. The design will exhibit suboptimal timing.
Running delay-based LUT packing...
Updating timing models...
ERROR:Map:237 - The design is too large to fit the device. Please check the
Design Summary section to see which resource requirement for your design
exceeds the resources available in the device. Note that the number of slices
reported may not be reflected accurately as their packing might not have been
completed.

Mapping completed.
See MAP report file "minsoc.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors : 1
Number of warnings : 3

Could it be that the minsoc soft core is really simply too big for my board?

What are the usual specs required to run it ? How many LUTs, etc?

Can I disable some parts? Well, there is no point in running a softcore CPU that takes up 90% of my FPGA resources and leaves me with 10% for applications ...

Thanks

Ulrich

Ulrich Staudinger

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May 28, 2012, 3:47:38 PM5/28/12

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Welllllllllllll,

So ....

I disabled eth, uart and also dbg. Which didn't work. I reenabled dbg. So, just or1200 and dbg.

Let's make it short:

==========

from minsoc_top:

Design Summary Report:

Number of External IOBs 9 out of 372 2%

Number of External Input IOBs 4

Number of External Input IBUFs 4

Number of LOCed External Input IBUFs 3 out of 4 75%

Number of External Output IOBs 5

Number of LOCed External Output IOBs 1 out of 5 20%

Number of External Bidir IOBs 0

Number of BSCANs 1 out of 1 100%

Number of BUFGMUXs 2 out of 24 8%

Number of DCMs 1 out of 8 12%

Number of MULT18X18SIOs 4 out of 20 20%

Number of RAMB16BWEs 12 out of 20 60%

Number of Slices 5325 out of 5888 90%

Number of SLICEMs 32 out of 2944 1%

Overall effort level (-ol): High

==========

bitgen then fails.

I think minsoc is great and could be very well suitable for many applications. But my spartan3an is simply not able to run it unless some miracle happens.

just for the sake of completion, following the bitgen complains.

>.