Ad9361 No Os Driver

[Maryetta Worm]

Thereare configuration options that must be set properly.Some others allow you to set defaults, but can be changed anytime later using the driver API.But most of these options don't need to be changed at all.

This is a Linux industrial I/O (IIO) subsystem driver, targeting RF Transceivers.The industrial I/O subsystem provides a unified framework for drivers for many different types of converters and sensors using a number of different physical interfaces (i2c, spi, etc).See IIO for more information.

Each and every IIO device, typically a hardware chip, has a device folder under /sys/bus/iio/devices/iio:deviceX.Where X is the IIO index of the device. Under every of these directory folders reside a set of files, depending on the characteristics and features of the hardware device in question. These files are consistently generalized and documented in the IIO ABI documentation. In order to determine which IIO deviceX corresponds to which hardware device, the user can read the name file /sys/bus/iio/devices/iio:deviceX/name. In case the sequence in which the iio device drivers are loaded/registered is constant, the numbering is constant and may be known in advance.

Because of differences in silicon implementation; and the way an IIO device wants to be expressed as a device with channels and attributes, there may be specific attributes that are exposed on multiple channels, that control the same bit/register in the device (are duplicated for convenience or to match the IIO model). A specific example of this is:

The AD9361 transceiver contains two identical RFPLL synthesizers to generate the required LO signals.One is programmed for the RX channel and the other for the TX channel.The tuning range supported by this driver covers 70MHz to 6GHz (AD9363: 325-3800 MHz) with 2Hz tuning granularity.

If both, the TX and RX Local Oscillators (LO) are set to the same frequency or very close to each other.The TX LO may leak into the RX path. Usually this is avoided in TDD mode, since always only one of the LOs is enabled at a given time. However sometimes it can be beneficial in FDD mode to turn the TX LO off. Care must be taken since TX LO in Power-down mode, will cause the TX QUAD calibration to fail.

The driver allows switching between external and internal LO on the fly.Writing 1 into out_altvoltage0_RX_LO_external/out_altvoltage1_TX_LO_external switches to external LO.Respectively writing 0 switches back to the internal synthesizer.

When in fastlock pin select mode (adi,[txrx]-fastlock-pincontrol-enable).This file needs to be written once with a value, before the pin-control can be used.This will moves the device into fastlock mode.

The AD9361 RX signal path passes downconverted signals (I and Q) to the baseband receiver section. The baseband RX signal path is composed of two programmable analog low-pass filters, a 12-bit ADC, and four stages of digital decimating filters. Each of the four decimating filters can be bypassed. The corner frequency for each low-pass filter is programmable via SPI registers. Figure below shows a block diagram for the AD9361 RX signal path. Note that both the I and Q paths are schematically identical to each other.

The high level in_voltage_sampling_frequency attribute effectively controls the BBPLL frequency the ADC Sample clock and all following decimating filter blocks except the FIR block which is handled upon user configuration.This IIO device attribute allows the user to control the Baseband (BB) Sample Rate in Hz granularity in the range from 521KSPS up to 61.44MSPS, also depending on the FIR filter decimation chosen.in_voltage_sampling_frequency as well as out_voltage_sampling_frequency are not entirely independent, by default the both need to match unless adi,fdd-rx-rate-2tx-enable is enabled.Then RX rate can be twice the TX rate.

The high level out_voltage_sampling_frequency attribute effectively controls the BBPLL frequency the ADC Sample clock, the DAC clock and all following interpolation filter blocks except the FIR block which is handled upon user configuration.This IIO device attribute allows the user to control the Baseband (BB) Sample Rate in Hz granularity in the range from 218KSPS up to 61.44MSPS, also depending on the FIR filter decimation chosen.out_voltage_sampling_frequency as well as in_voltage_sampling_frequency are not entirely independent, by default the both need to match unless adi,fdd-rx-rate-2tx-enable is set.Then RX rate can be twice the TX rate, however this mode needs to be supported by the FPGA/Baseband-Processor.The feedback clock must be externally divided.

To enable or disable the RX or TX path filters simply write 0,N or 1,Y to one of belowcontrol files. Combo attribute in_out_voltage_filter_fir_en allows to simultaneously enable both filters.This might sometimes be necessary, depending on the RX/TX Path Sampling Frequency and FIR interpolation and decimation rates chosen.

The AD9361 features several Rx Analog Filter Blocks (RX TIA LPF, RX BB LPF)Analog filtering before the ADC reduces spurious signal levels by removing mixer products and providing general low pass filtering prior to downconversion.The RX TIA LPF is a single-pole low-pass filter with a programmable 3dB corner frequency.The RX BB LPF is a third-order Butterworthlow-passfilter with a programmable 3dB corner frequency.

The AD9361 features several Tx Analog Filter Blocks (TX BB LPF, TX Secondary LPF)Analog filtering after the DAC reduces spurious outputs by removing sampling artifacts and providing general low pass filtering prior to upconversion.The TX BB LPF is a third-order Butterworth low-pass filter with a programmable 3dB corner frequency.The TX Secondary LPF is a single-polelow-passfilter with a programmable 3dB corner frequency.

The versatile and highly configurable AD9361 transceiver has several gain control modes that enable its use in a variety of applications. Fully automatic gain control (AGC) modes are available that address time division duplex (TDD) as well as frequency division duplex (FDD) scenarios. In addition, the AD9361 has manual gain control (MGC) options that allow the baseband processor (BBP) to control the gain.

The default ADI provided optimized gain tables in full table mode provide 77 entries and in split gain table mode 41.Each index results typically in a 1 dB monotonic gain step. There are a total of 3 different tables available for different RX LO frequency ranges. The tables are swapped in and out automatically by the driver based on RX LO settings.

Custom gain tables can be loaded automatically during driver probe or anytime later via the gain_table_config sysfs attribute.Tables must be stored in the /lib/firmware folder, or compiled into the kernel using the CONFIG_FIRMWARE_IN_KERNEL, CONFIG_EXTRA_FIRMWARE config options.The table loaded during driver probe can be specified using following device tree property:

The TX attenuation/gain can be individually controlled for TX1 and TX2.The range is from 0 to -89.75 dB in 0.25dB steps.The nomenclature used here is gain instead of attenuation, so all values are expressed negative.

Given the wide variety of applications for which the AD9361 is suited, the received strength signal indicator (RSSI) may be setup in one of several configurations, allowing the user to optimize the RSSI to produce extremely accurate results with a minimum of BBP interaction. The AD9361 measures RSSI by measuring the power level in dB and compensating for the receive path gain. The various options available support both TDD and FDD applications. Note that the RSSI value is not in absolute units. Equating the RSSI read-back value to an absolute power level (e.g., in dBm) requires a system factory or bench calibration. To calibrate the RSSI word to an absolute reference, inject a signal into the antenna port of the completed system and read the RSSI word. From this test, generate a correction factor that equates the RSI word to the injected signal level at the antenna port.

Recognizing that in TDD systems the receiver and transmitter are not operating simultaneously, the AD9361 provides the ability to reuse the receiver circuitry by multiplexing the power detector into the receive path. The receiver RSSI circuitry is then turned on during the transmit burst and results in accurate Tx RSSI measurements.

During device driver initialization the driver runs the RF DC offset calibration only on the default RF input port specified with these attributes.So if using the RF RX B or C inputs along with the RF RX A input, you should run the calibration also, once with other input band/port selected. After calibrating each band, switching between from the A input to the B or C input should not require another calibration unless a large frequency change is made. Since the B and C inputs use the same calibration results, switching from input B to input C may require running the RF DC offset calibration.

See here: Calibration Mode Controls: rf_dc_offs

During device driver initialization the driver runs the TX Quadrature calibration only on the default RF output port specified with these attributes.During regular operation TX Quadrature is only run on the select RF output. However the TX quadrature calibration stores a separate set of calibration results for the RF TX_A and TX_B output path. So if switching the output, the calibration must be once manually triggered.

See here: Calibration Mode Controls: tx_quad

The AD9361 can either be clocked from an external clock source or a local crystal oscillator (XO). Since it's likely that a Crystal oscillator is not perfect - a digital correction (DCXO) can be used to tune the external component. This only works with AT cut fundamental mode crystal resonators with a load capacitance of less than 10pF which are connected between the XTALP and XTALN pins of the AD9361.

By adjusting a capacitor within the AD9361, the resulting DCXO frequency can be adjusted to compensate for XO frequency tolerance and stability. dcxo_tune_coarse sets a coarse capacitor value while dcxo_tune_fine sets a fine capacitor value. Together, these two settings control the frequency of the DCXO. The resolution of the DCXO varies with coarse word with a worst case resolution (at coarse word = 0) of 0.0125 ppm. Using both coarse and fine words, the DCXO can vary the frequency over a 60 ppm range.

3a8082e126