Intel Serial Io Gpio Host Controller
Desiderato Merriwether
I have a motherboard with this controller, I have the pins wired out and I have the driver - but I cannot find any API or any information regarding how I can access this controller (or the pins) programmatically. Does anyone know where I can find a .net API, or any api or documentation for this?
Ultimately there is no question that it is an Intel GPIO chipset being used in this mainboard, and this is what I need assistance with.
I apologize if I posted it to the wrong channel - I just could not find any better option where to post me request.
If someone here can assist - great, if not, please point me to the correct place where this should be posted, and I'll be happy to post it on that channel.
Unfortunately I hit a brick wall with Intel and could not find anyone to talk to or any information about this controller. I would think that a company like intel would at least have some documentation that I could find - and if not, at least they should be helpful and point me in the right direction - but that is not the case.
For now, I had no choice but to use an external controller. I still have hopes that someone will be successful in finding this info and sharing it here so that I will be able to use the onboard controller.
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I/O Controller Hub (ICH) is a family of Intel southbridge microchips used to manage data communications between a CPU and a motherboard, specifically Intel chipsets based on the Intel Hub Architecture. It is designed to be paired with a second support chip known as a northbridge. As with any other southbridge, the ICH is used to connect and control peripheral devices.
As CPU speeds increased data transmission between the CPU and support chipset, the support chipset eventually emerged as a bottleneck between the processor and the motherboard. Accordingly, starting with the 2008 Intel 5 Series, a new architecture was used that incorporated some functions of the traditional north and south bridge chips onto the CPU itself, with the remaining functions being consolidated into a single Platform Controller Hub (PCH) and therefore replacing the traditional two chip setup.
The first version of the ICH was released in June 1999 along with the Intel 810 northbridge. While its predecessor, the PIIX, was connected to the northbridge through an internal PCI bus with a bandwidth of 133 MB/s, the ICH used a proprietary interface (called by Intel Hub Interface) that linked it to the northbridge through an 8-bit wide, 266 MB/s bus.
The Hub Interface was a point-to-point connection between different components on the motherboard. Another design decision was to substitute the rigid North-South axis on the motherboard with a star structure.
Note that, along with the ICH, Intel evolved other uses of the "Hub" terminology. Thus, the northbridge became the Memory Controller Hub (MCH) or if it had integrated graphics (e.g., Intel 810), the Graphics and Memory Controller Hub (GMCH).
In early 2000 Intel had suffered a significant setback with the i820 northbridge. Customers were not willing to pay the high prices for RDRAM and either bought i810 or i440BX motherboards or changed to the competition. The hastily developed 82815 northbridge, which supported PC-133 SDRAM, became Intel's method to recover in the middle range segment.
In 2001, Intel delivered ICH3, which was available in two versions: the server version, ICH3-S, running with the E7501 Northbridge, and the mobile version, ICH3-M, which worked with the i830 and i845 northbridges. There is no version for desktop motherboards.
In comparison with the ICH2, the changes were limited: "Native Mode" support in the PATA Controller; up to six USB-1.1 devices; SMBus 2.0; and the newest SpeedStep version, which allowed power-saving devices to be switched off during operation. The chip had 421 pins.
The ICH4 was Intel's southbridge for the year 2002. The most important innovation was the support of USB 2.0 on all six ports. Sound support was improved and corresponded the newest AC'97 specification, version 2.3. Like the preceding generation, the ICH4 had 421 pins.
In 2003, and in conjunction with the i865 and i875 northbridges, the ICH5 was created. A SATA host controller was integrated. The ICH5R variant additionally supported RAID 0 on SATA ports. Eight USB-2.0 ports were available. The chip had full support for ACPI 2.0. It had 460 pins.
Since 1999 the 266 MB/s hub interface was assumed to be a bottleneck. In the new chip generation, Intel therefore offered an optional port for a Gigabit Ethernet Controller directly attached to the MCH.
The goal of this CSA technology was to reduce the latencies for Gigabit LAN by direct memory access and to free up bandwidth on the Hub interface between ICH and MCH for non removable disk and PCI data traffic.
In particular, when connecting USB devices via front panels, the chips died by discharges of static electricity. Intel reacted to the problem by shipping ICH5 with increased ESD tolerance. Effective ESD preventive measures on USB ports are difficult and costly, since they can impair the quality of the USB-2.0 high-speed signals. Many motherboard manufacturers had omitted the necessary high-quality safety devices for front panel connectors for cost reasons.
ICH6 was Intel's first PCI Express southbridge, to pair with the i910 and i915 MCH. It made four PCI Express 1 ports available. Faster 16-Ports were accommodated in the MCH. The bottleneck Hub interface was replaced by a new Direct Media Interface (in reality a PCI Express 4 link) with 1 GB/s of bandwidth per direction. Support for Intel High Definition Audio was included. In addition, AC'97 and the classical PCI 2.3 were still supported.
ICH6R and ICH6-M implemented AHCI SATA controllers for the first time. The chips had 652 pins. Originally Intel had planned to bring two further variants under the names ICH6W and ICH6RW to the market, which should contain a software Access Point for a Wireless LAN. These chips are published.
ICH8 is offered in several different versions and is the complement to the 965 class MCH chips. The non-mobile ICH8 does not have a traditional PATA interface, and just one AC'97. In practice, most baseboard manufacturers still offered PATA appropriate connection types using additional chips from manufacturers such as JMicron or Marvell.
The ICH9 came out in May 2007 in the P35 (Bearlake) chipset. It removes all PATA support. In practice, many motherboard manufacturers continue providing PATA support using third-party chips. Officially only the ICH9R, ICH9DH, ICH9DO chip have AHCI support.
As CPU speeds increased, a bottleneck eventually emerged between the processor and the motherboard, due to limitations caused by data transmission between the CPU and southbridge. Accordingly, starting with the Intel 5 Series, a new architecture was used where some functions of the north and south bridge chips were moved to the CPU, and others were consolidated into a Platform Controller Hub (PCH).
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