what does the DMA burst mean?

[johndoe]

for example, DMA burst size 2k, what does it mean?

sorry for this kind of question.

thanks.

[Kerem Gümrükcü]

Hi,

read this:

http://en.wikipedia.org/wiki/Burst_mode_(computing)
http://en.wikipedia.org/wiki/Direct_memory_access

Read all of both, then you will know,...

Regards

K.

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Kerem Gümrükcü
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"johndoe" <joh...@microsoft.com> schrieb im Newsbeitrag
news:OMXlrsZo...@TK2MSFTNGP04.phx.gbl...

[amor...@ieee.org]

A burst transfer, in hardware terms, is a data transfer where upfront
knowledge of certain factors - such as physical memory addresses being
incremented sequentially - allow the hardware circuitry to use a
shortened cycle for all but the first transfer, thus achieving higher
throughput at the cost of hogging up the transfer medium (such as a
bus) for the duration of the transfer.

Bursts are extensively used in memory technology and are not limited
to dma. For example, sometimes people say that a dynamic ram performs
"8-2-2-2" at a given clock frequency, meaning that it can transfer
information in bursts of four units (whatever the bus width of the
memory permits): the first transfer takes 8 clock cycles, but the next
three only take 2 cycles each. Try for example,
http://www.pcguide.com/ref/mbsys/bios/set/advchDRAMWrite-c.html.

Dma typically relies on the ability of a bus to accomodate multiple
hosts. Before you can do dma, you must go through an "arbitration"
cycle, so that your peripheral and no one else now "owns" the bus.
After this arbitration, you can issue one word and relinquish the bus,
or you can "burst" a number of words, meaning, you transfer the words
without going through another arbitration phase.

Note that while you're bursting a dma on a bus, nobody else can access
the bus. In order to avoid peripherals hogging the bus for extended
periods of time - avoiding for example sound breakdown while a disk
transfer or a complex rendering is taking place - many buses implement
watchdog protocols that limit the maximum size of a transfer.

So, if you have a 2K dma burst size, it means that after an initial
arbitration cycle gives your peripheral control of the bus, it will
transfer 2k bytes (or dwords, or whatever your unit of counting
happens to be) before relinquishing control.

This is mostly a hardware subject. If you want more detail, maybe you
could peruse the PCI bus standard, or just take a peek at a dma
controller's spec - for example, you can try
http://www.st.com/stonline/products/literature/anp/12729.pdf, or just
google for "dma burst".

Hope this helps,

Alberto.

[Maxim S. Shatskih]

1 address cycle over the bus and then lots of consecutive data cycles to transfer 2K

--
Maxim S. Shatskih
Windows DDK MVP
ma...@storagecraft.com
http://www.storagecraft.com

"johndoe" <joh...@microsoft.com> wrote in message news:OMXlrsZo...@TK2MSFTNGP04.phx.gbl...

[Maxim S. Shatskih]

>to dma. For example, sometimes people say that a dynamic ram performs
>"8-2-2-2" at a given clock frequency, meaning that it can transfer
>information in bursts of four units (whatever the bus width of the
>memory permits): the first transfer takes 8 clock cycles, but the next
>three only take 2 cycles each. Try for example,

It's much more complex, but the first not-so-exact approach for this is yes, correct.

>hosts. Before you can do dma, you must go through an "arbitration"
>cycle,

PCI arbitration is "hidden" and does not consume cycles. The bus release from the previous cycle does consume some time though.

[amor...@ieee.org]

Dma Arbitration is required before you can transfer data, even if it
is pipelined with an earlier data cycle. It may not cost throughput,
but it will cost latency.

Alberto.

On Mar 12, 4:52 pm, "Maxim S. Shatskih"