>However we made your card
>with no errors so long
It isn't a problem using a single interface or a few GPIO pins; only
when you make fuller use of the available functionality. You can make
it work with 2-layers with careful design and if you don't demand too
much from the chip.
>correct way to do isolation in 4 layers
Take a look at the following simple design for an isolator that
takes into account most of the AppNote suggestions related to the
ADuM6401 which offers 5kV of isolation:
http://www.analog.com/en/interface/digital-isolators/adum6401/products/product.html
http://code.google.com/p/opendous/source/browse/trunk/Current_Designs/Isolator/
On Sep 23, 11:28 am, uros <
uros.petrev...@gmail.com> wrote:
> Thanks for these important details. However we made your card with no
> errors so long, but we didn't test ethernet yet! I'm really interested
> in going further with this processor for now. Do you have some
> documentation about correct way to do isolation in 4 layers?? I'll be
> really grateful. Your card has really good features so I think of
> redesigning it in 4 layers, and of course sharing it.
> I have one mBed card that has the same proc for exemple, and it's 4
> layer PCB, so you are right, 4 layer is necessary for this procs.
>
> I was working also on toolchain with Drasko, we think that we can make
> makefile more simple and clear to use. For now i'm compiling for your
> board with makefile that is used to rebuild mbed project and it's
> fairy simple. Did you look at :
http://dev.frozeneskimo.com/notes/compiling_your_own_cmsis_code_for_t...
>
> specially if you are working with other systems than windows (we are
> on os x and linux). In every case it's a good start to make a makefile
> for this architecture...
>
> Best,
> uros
>
> On Sep 12, 7:33 pm, "Opendous Inc." <
opend...@gmail.com> wrote:
>
> > Unfortunately, the board does have issues. JTAG drops out randomly,
> > Ethernet sends out packets only once in a while, and I have fried a
> > couple of the ICs with ESD even though I am incredibly careful and
> > have ESD mats and wrist straps. Without a proper GND plane the high
> > speed IO creates too much GND bounce that even mass amounts of
> > decoupling capacitors cannot fix as the long GND leads act to increase
> > capacitor inductance.
>
> > I tried the 2-layer thing but have concluded there is not much
> > chance of getting anything reliable and have moved on to a proper 4-
> > layer design. Due to the added cost I figure I may as well get HS-USB
> > and have decided on the LPC18xx. You can follow my progress:
http://code.google.com/p/micropendousx/source/browse/trunk/Micropendo......