RLL & ESDI

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e2k

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Jul 10, 2023, 11:02:10 AM7/10/23
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Could it work for RLL and ESDI too?
I see that there were some experiments with RLL, and once ESDI got mentioned, ...
Any insight?
THANKS

Al Kossow

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Jul 10, 2023, 12:21:49 PM7/10/23
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On 7/10/23 8:02 AM, e2k wrote:
> Could it work for RLL and ESDI too?
> I see that there were some experiments with RLL, and once ESDI got mentioned, ...

I have samples of RLL and MFM encoding here if someone wants to look at writing an RLL decoder
One of the problems is there is little documentation on how various chipsets did RLL encoding
http://bitsavers.org/projects/hd_samples

ESDI drives use a different physical interface so the existing board cannot work with them.

David Gesswein

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Jul 10, 2023, 12:54:31 PM7/10/23
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Their was one person looking at adding RLL support but haven't heard anything
in a while so suspect they decided it was too much. RLL has been something
I've wanted to add but hasn't made it to the top of the project list. Have
gotten more questions on it recently but not going to have a large enough
chunk of free time to think about doing it until end of year. If someone does
want to look at doing it I can support them.

e2k

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Jul 10, 2023, 1:13:47 PM7/10/23
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So, the RLL should work, it is "just" a matter of the right software.
Looking at ESDI, it also has the clock signal on the connectors, drivers are faster, but it is similar/upgrade to the ST506 interface?
So one could upgrade the existing HW by few signals and also support ESDI?
Am I completely wrong, or too naïve?

Cheers

David Gesswein

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Jul 10, 2023, 1:24:55 PM7/10/23
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I don't think ESDI is possible with the beaglebone. Data rate is 20 MHz or
so which you could do with a SPI port but there were other signals such as
sector start that needed to be accuratly generated relative to the data
stream. I couldn't figure out any way to do that with beaglebone. Details are
fuzzy now since I looked at it 9 years ago when I started this project. Didn't
think it had been that long. Time flies when your involved in too many things.
PRU isn't fast enough to deal with 20 MHz data without using SPI port.

On Mon, Jul 10, 2023 at 10:13:47AM -0700, e2k wrote:
> So, the RLL should work, it is "just" a matter of the right software.
> Looking at ESDI, it also has the clock signal on the connectors, drivers
> are faster, but it is similar/upgrade to the ST506 interface?
> So one could upgrade the existing HW by few signals and also support ESDI?
> Am I completely wrong, or too naďve?
>
> Cheers
>
> On Monday, 10 July 2023 at 12:21:49 UTC-4 a...@bitsavers.org wrote:
>
> > On 7/10/23 8:02 AM, e2k wrote:
> > > Could it work for RLL and ESDI too?
> > > I see that there were some experiments with RLL, and once ESDI got
> > mentioned, ...
> >
> > I have samples of RLL and MFM encoding here if someone wants to look at
> > writing an RLL decoder
> > One of the problems is there is little documentation on how various
> > chipsets did RLL encoding
> > http://bitsavers.org/projects/hd_samples
> >
> > ESDI drives use a different physical interface so the existing board
> > cannot work with them.
> >
> >
>
> --
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PC-maniak

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Jul 10, 2023, 1:39:30 PM7/10/23
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Hi the attempt to add RLL support was mine .. unfortunately I did not progress at all .. there is very little free time for it.. sorry

po 10. 7. 2023 v 19:24 odesílatel David Gesswein <d...@pdp8online.com> napsal:

e2k

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Jul 11, 2023, 5:27:55 AM7/11/23
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Where could I find documentation of the format of those binary files?


On Monday, 10 July 2023 at 12:21:49 UTC-4 a...@bitsavers.org wrote:

d...@pdp8online.com

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Jul 11, 2023, 4:48:06 PM7/11/23
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.ex files is a raw image of the disk for Unix folks equivalent to dd if=/dev/disk of=file.ex. This is what I call extracted data file. If this file exists my tools can already decode the disk.

.tr is time samples between rising edges of the data line from the drive. Each track starts and ends when mfm_read sees index pulse. This is what I call transitions file.

In my code emu_tran_file.c will read the transitions file and tran_file_read_track_deltas will convert a track to time deltas. Deltas are returned in 200 MHz clock counts.
Comments in the .c file give some more information on the format.

Let me know where you need more detail.
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