Follow-up: Seeking Alpha-testers for HDL Forever

[andrew]

Hello all,

I've been working on an IDE for HDL Engineers over the past few months. The goal of the tool is to make it easy for engineers to move between different FPGA designs/toolchains with one unified IDE.

The tool offers a minimal interface and code indexing features for VHDL/Verilog. With fast synth/P&R toolchains, development feels as quick and simple as Arduino. The tool can detect and configure environment for Xilinx, Altera, Microchip, Gowin, and Lattice FPGAs.

If you are interested in trying it, send me a message and I’ll get in touch.

See demo enclosed:

https://www.loom.com/share/6483f0b4c121447183f1b6179b843f23

Thanks,

Andrew

[cameron.eda]

If anyone is interested in better simulators for FPGA projects, I'm working on translating RTL level SystemVerilog to run in NVC with Claude-Code's help, that should be faster than VCS if we do it right (at least in debug).

A phase 2 of the project would be getting it to work natively on FPGA's (RTL->LUTs with YoSys or http://HotWright.com).

Alpha-testers or just test RTL code appreciated.

Note: if you use Altera or Xilinx's simulators, I'd be interested in benchmarking performance.

https://chipletsummit.com/proceeding_files/a0q5f0000044zma/20240206_PreConG_Cameron.PDF

Kev.

[Yuri Panchul]

If you want to test SystemVerilog translation for simulation, you can get an example from one of our repos, for example this self-checking test:

https://github.com/verilog-meetup/basics-graphics-music/tree/main/labs/4_microarchitecture/4_2_fifo/4_2_9_a_plus_b_using_wrapped_fifos

Thank you,

Yuri Panchul

--
You received this message because you are subscribed to the Google Groups "SystemVerilog Meetups in Silicon Valley" group.
To unsubscribe from this group and stop receiving emails from it, send an email to meetsv+un...@googlegroups.com.
To view this discussion visit https://groups.google.com/d/msgid/meetsv/5b7e9535-e2ab-4fb3-97bc-ae8c6d642ba5n%40googlegroups.com.