Alpha-testing a new GUI for SystemVerilog + FPGA development created by Andrew DeKelaita

[yuri.panchul]

Colleagues:

During the next Verilog Meetup on Sunday December 7 we are going to alpha-test a new tool which aims to "arduinize FPGAs", i.e. remove the barrier to entry for the SystemVerilog / FPGA development. The tool is created by Andrew DeKelaita, an experienced FPGA designer. Claims to fame:

1. Minimalistic interface in the "beginner mode" when working with the examples from the BGM (basics-graphics-music) repository. Unlike busy interfaces in Vivado, Quartus, VS Code with plugins etc.

2. Short edit-compile-run cycle with a single button, unlike tedious web-based CI/CD GitHub-action-based environments with downloading bitstream from the web.

3. The environment detects a board automatically when you plug it in. We do it for multiple Xilinx, Altera, Gowin and Lattice boards.

The tool also provides source code indexing and other features for advanced users.

Alpha testing will be at the Verilog Meetup on Sunday December 7 from 11 am to 2 pm at Hacker Dojo, 855 Maude Ave, Mountain View, California. We are bringing a bunch of boards and a dozen computers, so you just need to bring your brains. You also need to donate $20 to Hacker Dojo since we are using their space.

Thank you,

Yuri Panchul