The focus of the next three meetups is RISC-V examples for the textbook and the training in India

[Yuri Panchul]

We are going to try a new format of Verilog Meetup starting this Sunday. During the last two years the main format was to show new members or just curious people an intro presentation and FPGA demos.

The new format will be more focused meetings to prepare code for two other projects:

1. A textbook written in collaboration with Purdue University. The initial participants were Yuri Panchul and Dmitri Gusev (online). We are adding Allen Baker (Synopsys) and Ramprakash Baskar (Tesla) to work on it.

2. An embedded CPU on FPGA-based SoC training in India.

In addition we continue to work on beta-testing the GUI created by Andrew DeKelaita which can be used for the trainings in India, as well as for the discussed seminars in Florida and Boston.

Both (1) and (2) require creating a series of examples with small RISC-V cores to demonstrate the following aspects of CPU and SoC:

1. Integrating CPU with an external peripheral via AXI-based on-chip fabric.
2. The work of interrupts.
3. The work of caches, either internal or external to the core.
4. Pipeline forwarding, for pipeline cores.
5. Several cores sharing a common memory in a non-coherent way.

The claim to fame for our project will be that we support multiple cores (at the moment schoolRISCV, PicoRV32, YRV-Plus and APS from MIET) working on 40+ FPGA boards, as well as in simulation using Icarus Verilog, and compatible with the TinyTapeout infrastructure.

For the next three meetings we need to clean the following areas which are related to the software sides of the project:

1. We need to create a series of linker scripts, from trivial to more complicated examples that include interrupt service routines.

If you don't know what the linker script is, you can start from here:
https://mcyoung.xyz/2021/06/01/linker-script/

Please do not rely on AI in linker scripts, AI introduces embarrassing errors such as confusing BRAM and ROM. We need to analyze the linker scripts in many available RISC-V core examples (see for example https://github.com/yunchenlo/awesome-RISCV-Cores ), as well as in other educational projects, such as RVfpga and Wally OpenHW CPU. Then we need to come up with our set of linker scripts, compatible with our needs (small BRAM, interrupt handlers, possibly compatibility with RARS instruction set simulator).

2. We need to rewrite the existing makefiles to bash scripts in the style of other scripts in the basics-graphics-music (BGM) infrastructure. Please do not educate me that makefiles are good - I learn make 40 years ago, but you don't need make to manage the dependencies in something that takes a fraction of a second to run, such as:

xpack=/home/verilog/install/gccrv/xpack-riscv-none-elf-gcc-15.2.0-1
$xpack/bin/riscv-none-elf-gcc -march=rv32i_zbs_zicsr -mabi=ilp32 -ffreestanding -O3 -nostdlib -Tyrv.ld *.s *.c
$xpack/bin/riscv-none-elf-objcopy -O binary a.out final
python3 ../common/freedom-bin2hex.py -w32  final > code_demo.mem32

Bash scripting is more flexible than scripts inside Make (even GMake) and it is easier to support different variants of GCC and LLVM software toolchains for RISC-V if we go this route.

3. We need to understand RISC-V interrupt modes and come up with examples illustrating timer interrupts, interrupts from peripherals, such as SPI light sensor, and other cases (but not too deep, we don't need to build a sophisticated interrupt controller).

Here is a link to get some first clue:
https://starfivetech.com/uploads/sifive-interrupt-cookbook-v1p2.pdf

Thank you,
Yuri Panchul