Verilog Meetup updates

[Yuri Panchul]

I put the current activities in the post:

https://verilog-meetup.com/2025/08/28/status-2025-08-28/

You can see the video of the last discussion on the activities here:

https://youtu.be/hQWBsLWJQ2c

Two priorities:

1. Preparation for Maker Faire

2. Preparation for an event at CalPoly San Luis Obispo

Two new updates:

1. Creating the follow-up challenges to SystemVerilog microarchitecture challenge for AI No.1 and No.2 – Yuri Panchul, Aadithya Manoj and others. AI engines still struggle with No.2 but we need to prepare ahead the challenges No.3, 4 etc. They can present this work at the event at California Polytechnic State University in San Luis Obispo, California. The event is tentatively planned to the weekend of October 18.

2. Creating an open-source illustration and educational materials around cache coherency using the MSI protocol. Should allow the students to create transactions (reads, writes and interventions) and observe the sequence of actions: state changes, movement of data between L1 caches and the coherency manager, etc. Should include visualization via animation, RTL simulation support, ability to drive the transactions with or without CPU cores and a demo on FPGA boards. Nevil Pooniwala and Yuri Panchul. Status: brainstorming before the proposal.