The Verilog Meetup on November 9: two objectives

[Yuri Panchul]

We usually just discuss the ongoing projects or introduce new people to RTL methodology during the meetups on Sundays, however next Sunday there are two specific projects we need to do:

1. Sunday November 9 is the last day you can submit for the TinyTapeout shuttle SKY25B. We have a flow to convert our FPGA designs into ASIC designs using the methodology I described in 

https://verilog-meetup.com/2025/10/20/from-fpga-to-asic-using-template/

So Sunday is the day I can help other people to try their designs on FPGA boards, then resolve TT synthesis and lint issues and submit their design to manifacture an ASIC.

2. Several members (Maxim, Ram, Ruslan and others) were working for some time to support open-source-based toolchain for Lattice. We finally have a solution for the Icebreaker board, but we need to discuss, debug with all examples and polish it. This project is significant because these boards are now used at the University of California at Santa Cruz, which is a major university close to Silicon Valley, and UCSC students, Nathan Pham and Ethan James, use those boards for their classes.

So see you on Sunday,

Thank you,

Yuri Panchul