Developing new demos for Maker Faire Bay Area in Vallejo on September 25-27

[Yuri Panchul]

I already wrote that the Verilog Meetup is approved for Maker Faire Bay Area in Vallejo on September 25-27.

https://makerfaire.com/maker/entry/learn-chip-design-from-breadboards-to-fpga-to-your-own-asic-78900/

This is a large event with a lot of people, and I need a lot of help from everybody, particularly school students who did the projects.

For those who plan to help us at the show for more than 1 day, I recommend making hotel reservations now. I am going to stay in the Courtyard by Marriott Vallejo Napa Valley on September 24-27.

We have a month to prepare comprehensive presentations, the kits we recommend and demos.

I propose to develop the following set of new demos we are going to present in our booth at Maker Faire:

1. A small-scale integration chip design on a breadboard that computes a sequence of Fibonacci numbers and outputs them on a two-digit 7-segment display in hexadecimal form using DM9368. Requires two 4-bit adders 4008, 16 D-flip-flops (either 8 x 4013 or 4 x 4076 or 3 x 40174), two DM9368 and two seven-segment displays.

It is possible to initially create a 4-bit version, using a single 4008 adder, 8 D-flip-flops (either 4 x 4013 or 2 x 4076 or 2 x 40174), DM9368 and a seven-segment display.

This design should be demoed next to the equivalent design made using an FPGA.

I propose Timofei and Nil to work on this one.

2. A FIFO demo using 40105 FIFO chip, 4081 Quad 2-input AND gate, 4011 Quad 2-input NAND gate, two LEDs for FULL and EMPTY indication, 8-bit LED array for the write data and read data, 4 buttons for write data and 2 buttons for PUSH and POP. AND and NAND gates are needed to combine the clock with PUSH and POP to generate SHIFT IN and SHIFT OUT pulses that the 40105 uses to push and pop data.

References:

https://www.ti.com/lit/ds/symlink/cd74hct40105.pdf
https://www.ti.com/lit/ds/symlink/cd40105b-mil.pdf

https://habr.com/en/articles/646685/
https://habr.com/en/articles/713122/

This design should be also demoed next to the equivalent design made using an FPGA.

This design is important and I propose everybody work on it.

3. Two FIFO + Adder demo - a way to use FIFO to couple the addition arguments coming at different times.

I discussed this project with Maya.

4. Round-robin arbiter with two requests and two grants. An important design used to share resources between sub-blocks in a system of chip (SoC):

1) When Req0=1 and Req1=0, then combinationally Grant0=1 and Grant1=0. Grant is given to a single requestor.

2) When Req0=0 and Req1=1, then combinationally Grant0=0 and Grant1=1. Grant is given to a single requestor.

3) When Req0=0 and Req1=0, grant can be anything since it is not going to be used. We can set both Grant0 and Grant1 to 0.

4) When Req0=1 and Req1=1, the grant decision should be opposite to the previous grant decision. For example:

Clock cycle 0: Req 0,1 Grant 0,1
1: Req 0,0 Grant 0,0
2: Req 0,0 Grant 0,0
3: Req 0,0 Grant 0,0
4: Req 1,1 Grant 1,0
5: Req 1,1 Grant 0,1
6: Req 1,1 Grant 1,0
7: Req 1,1 Grant 0,1

This design is not trivial, it requires a D-Flip-Flop to keep the memory of the previous decision plus ~3 chips for AND/OR/NOT logic.

We can compare this design to the priority encoder design based on CMOS 4532.

It is also a good idea to implement this design using both SSI and FPGA.

Matvei with his father can work on this one, but eventually I want everybody to do this design. This design in SystemVerilog is one of my screening interview questions.

5. A combination of two FIFOs and an arbiter - a frequent design pattern. We can have this demo to impress design engineers from electronics companies that stop by our booth. There are two wow-factors: "Wow, it can be done using small-scale chips?" and "Wow, a school student did it?"

6. A Finite State Machine (FSM) to recognize the sequences (a code lock). The simplest one, and an FSM that recognizes 01, is described in Harris & Harris. I also put an article in Russian about it:

https://ddvca.com/2022/07/27/fsm-using-3-gens/

7. More advanced math-oriented project. Implement LFSR using both SSI and FPGA.

https://en.wikipedia.org/wiki/Linear-feedback_shift_register

There is also a good book in Russian, see pages 83-94:

https://math.ru/lib/book/djvu/bib-kvant-15/Kv30-83_Kodi_I_Matematika_M.N.Arshinov.djvu

8. CORDIC example recently implemented in Georgia on an FPGA.

9. A reference CPU demo: YRV+GCC+interrupts+task switching. I will share more details during the next meetups.

10. Two TinyTapeout demos with the designs that contain Verilog Meetup designs, including graphics and schoolRISCV CPU.

11. New board support: Gowin-based Brisbane Silicon board support package for basics-graphics-music, with Pmod LCD interface, TM1638 controller and LCD screen. Higher priority than other board support.

12. Demo with cameras: TangNano 4K and/or 9K with OV2640 camera, or some Altera board with OV7670 camera.

Older demos:

13. LED matrix display and Tang Primer 25K board.

14. Note recognition and synthesis on Omdazz and other FPGA boards.

15. Geiger-Muller radiation counter connected to FPGA.

16. Graphical games.

Thank you,
Yuri Panchul