Reviewing the output of an AI EDA tool that generates SVA
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Yuri Panchul
Dec 25, 2025, 8:18:15 PM12/25/25
to SystemVerilog Meetups in Silicon Valley
Review video: https://youtu.be/0z13arpzrT4
Abhishek Varma, MS in VLSI & Microelectronics, from Illinois Institute of Technology, created an AI EDA tool that generates SystemVerilog Assertions (SVA).
https://www.linkedin.com/in/abhishekvarma10/
Yuri Panchul asked Abhishek Varma to run his tool on his open-source SystemVerilog example of an AXI-Lite Verification IP that contains a master BFM (Bus Functional Model) and a reference slave.
In this video Yuri reviews the results of Abhishek's tool run. This video also might be useful for those who want to learn AXI protocol, especially its valid/ready handshaking, pipelining and out-of-order with tags feature.
Abhishek Varma, MS in VLSI & Microelectronics, from Illinois Institute of Technology, created an AI EDA tool that generates SystemVerilog Assertions (SVA).
https://www.linkedin.com/in/abhishekvarma10/
Yuri Panchul asked Abhishek Varma to run his tool on his open-source SystemVerilog example of an AXI-Lite Verification IP that contains a master BFM (Bus Functional Model) and a reference slave.
In this video Yuri reviews the results of Abhishek's tool run. This video also might be useful for those who want to learn AXI protocol, especially its valid/ready handshaking, pipelining and out-of-order with tags feature.
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