DDR4 Implementation and Verification RTL Assistance

[Stanley To]

Hello all,

I am working on my Master's degree at Cal Poly, and my thesis involves the implementing a CPU core that interfaces with DDR4 memory in RTL using Vivado to implement on AMD's Virtex UltraScale+ FPGAs.

I am currently working with the RVComp (https://github.com/archlab-sciencetokyo/) academic FPGA core developed by Science Tokyo's Kise Laboratory that supports DDR2 and DDR3 using the MIG-7 memory interface generator.

Is there someone with some experience I can talk to in regards to any of these following issues:

1. FSM Operation: Is there any operational changes between DDR3 and DDR4 that require adding or redesigning an existing FSM to explicitly refresh data? It seems the pin layout changed and the changes added new banks, but I'm not sure if I can keep some of the existing FSM structure in the existing DRAM controller.
2. Verification: How can I verify DDR4 operation on Vivado or any open-source tooling? The Micron board models found online work with VCS and ModelSim, but my university does not have a partnership with those companies to provide me academic access to those.

Any assistance would be greatly appreciated.

Thanks,

Stanley To