Verilog Meetup at Cal Poly report

[Yuri Panchul]

https://verilog-meetup.com/2025/10/29/calpoly-slo-report/

A push for better workforce development in EE starts with the Verilog Meetup at Cal Poly San Luis Obispo

The idea to make a Verilog Meetup event at California Polytechnic State University, San Luis Obispo, started as a discussion between Yuri Panchul, a chip designer, and Stanley To, a CalPoly EE graduate working as an airspace contractor. This happened during an OpenSauce exhibition in the San Francisco Bay Area back in the summer. The discussion was joined by several student activists and the topic was the following:

It is not a secret to anybody in the digital chip design industry that students in many schools are not trained in solving microarchitectural problems with pipelines, FIFOs, credit-based flow control, arbiters etc, which constitute the bulk of work in front-end RTL design in the industrial projects: GPU, networking chips etc.

In a school, students usually have a Verilog class with FPGA labs that goes from gates to FSMs, plus a computer architecture class that presents the only kind of pipeline they know: a traditional 5-stage static pipeline for RISC-V (and MIPS in the past). This is not enough to work productively or even to pass a job interview, because many companies ask candidates questions on data pipelining.

So we decided to make an event to start the process of repairing the education system to better align it with industrial needs. To make the event more complete, we added a lecture on static timing analysis to microarchitecture, since designing a perfect pipeline should go along with measuring how many picoseconds are left in each stage we are building, and balancing the pipeline latency versus the maximum clock frequency.

Since learning digital design without doing is similar to learning to play a flute by watching slides on how to press the flute keys, we added FPGA boards and a path to move the design to a manufactured ASIC to our event.

We also covered Built-In Self-Test (BIST), memory repair with BIRA and BISR, a bit of emulation, and a talk on challenging AI. We tried to make FPGA exercises more fun by generating graphics on LCD screens. Then we also planned work work with music, but ran out of time.

All videos - see the link above

[Stanley To]

Thanks everyone who attended and contributed!

Yuri, thanks for bringing the Gowin hardware for us to play around with.

Alex, Henry, and Francisco: Thanks for the presentations because we absolutely learned a lot. Most students taking computer architecture classes have not even heard or seen anything resembling a credit-based control flow before, so it is nice to hear Alex's presentation on it. It's only been a few months since I last saw Henry and Francisco since they graduated from Cal Poly, but it feels like there's so much more we can and should learn from the design industry.

I'll have to figure out how to explain some of these concepts to younger students in smaller presentations during my final year at Cal Poly to other budding computer architecture enthusiasts to ensure the knowledge gets taught (and to make it less of a miracle to have companies recruit American college students for digital design and design verification jobs).

Hopefully next time around an event like this occurs in the future, we can get more people to come.