Plan for the Summer
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Yuri Panchul
May 14, 2026, 3:15:02 AMMay 14
to SystemVerilog Meetups in Silicon Valley
Plan for the Summer
for the Verilog Meetup and the related open source projects
Yuri Panchul, 2025-05-13
The projects:
for the Verilog Meetup and the related open source projects
Yuri Panchul, 2025-05-13
The projects:
1. Embedded CPU on FPGA. This is a request from India, well aligned with other needs. In addition to the existing schoolRISCV CPU example in the BGM repository, we are going to support three other cores: PicoRV32, YRV and APS. The support includes an option to program all cores in C and a demo for interrupts.
2. A proper systolic array example with matrix multiplication, ported to larger FPGA boards, such as Terasic DE23-Lite, Tang Mega 138K Pro and others.
3. DSP examples, filtering and FFT using the exercises with sound as a base.
4. More CPU-related microarchitectural examples, such as the reorder buffer, scoreboard, Tomasulo and (eventually) branch predictors.
5. A proper UART example, should be compatible with multiple terminals (putty, tio, screen, cu, picocom, minicom), all the platforms (Linux, Windows, Mac) and reusable for loading programs to CPU and the systolic array example.
6. Writing a textbook in cooperation with Purdue University.
7. LibreLane support. The initial support is already implemented by Jason, a UC Santa Cruz student, but we need to make it also compatible with the AppImage installation, not just “nix develop” mode. I also have a couple of cosmetic suggestions on how to run it without starting a new shell. But the bulk of the work is to make all the code in the BGM repo to be compatible with this flow. This work can be distributed among several people.
8. Gowin-based Brisbane Silicon board support package for basics-graphics-music, with Pmod LCD interface, TM1638 controller and LCD screen. Higher priority than other board support.
9. A set of breadboard examples with small-scale ICs. Can be used as a prequel to FPGA training or for children's education.
10. Short seminars in different countries. In addition to India, we are considering UK, Georgia, Kazakhstan, Uzbekistan. If there is somebody who can support a seminar in China or Vietnam, we can discuss it as well.
11. Local events in Mountain View, San Francisco, maybe events in Florida or other places.
12. Checking all the currently supported boards with new versions of EDA software (Xilinx, Altera, Gowin, OSS for Lattice).
A top priority is to create a reference CPU demo: YRV+GCC+interrupts. Once it is done and polished, the next top priority is to do this for APS and PicoRV32. Once we have three reference examples, we add other embedded CPU-related examples. The challenges include making proper memory maps / linker scripts, interrupt controllers and UART integration.
See https://verilog-meetup.com/about/
2. A proper systolic array example with matrix multiplication, ported to larger FPGA boards, such as Terasic DE23-Lite, Tang Mega 138K Pro and others.
3. DSP examples, filtering and FFT using the exercises with sound as a base.
4. More CPU-related microarchitectural examples, such as the reorder buffer, scoreboard, Tomasulo and (eventually) branch predictors.
5. A proper UART example, should be compatible with multiple terminals (putty, tio, screen, cu, picocom, minicom), all the platforms (Linux, Windows, Mac) and reusable for loading programs to CPU and the systolic array example.
6. Writing a textbook in cooperation with Purdue University.
7. LibreLane support. The initial support is already implemented by Jason, a UC Santa Cruz student, but we need to make it also compatible with the AppImage installation, not just “nix develop” mode. I also have a couple of cosmetic suggestions on how to run it without starting a new shell. But the bulk of the work is to make all the code in the BGM repo to be compatible with this flow. This work can be distributed among several people.
8. Gowin-based Brisbane Silicon board support package for basics-graphics-music, with Pmod LCD interface, TM1638 controller and LCD screen. Higher priority than other board support.
9. A set of breadboard examples with small-scale ICs. Can be used as a prequel to FPGA training or for children's education.
10. Short seminars in different countries. In addition to India, we are considering UK, Georgia, Kazakhstan, Uzbekistan. If there is somebody who can support a seminar in China or Vietnam, we can discuss it as well.
11. Local events in Mountain View, San Francisco, maybe events in Florida or other places.
12. Checking all the currently supported boards with new versions of EDA software (Xilinx, Altera, Gowin, OSS for Lattice).
A top priority is to create a reference CPU demo: YRV+GCC+interrupts. Once it is done and polished, the next top priority is to do this for APS and PicoRV32. Once we have three reference examples, we add other embedded CPU-related examples. The challenges include making proper memory maps / linker scripts, interrupt controllers and UART integration.
See https://verilog-meetup.com/about/
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