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Most people says that a failed CAS cost much less then one that succeed, but just like a load or more?
Probably the success will cause invalidation of all the caches that reference the cache line changed, but the failed case should lock (on x86) it and AFAIK locks (hw or SW) are not well known to be scalable and performant :)
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Hi,
On Sat, Sep 14, 2019 at 8:28 PM Vitaly Davidovich <vit...@gmail.com> wrote:
>
> Unlike C++, where you can specify mem ordering for failure and success separately, Java doesn’t allow that. But, the mem ordering is the same for failure/success there. Unfortunately it doesn’t look like the javadocs mention that,
Unfortunately so.
> but I recall Doug Lea saying that’s the case on the concurrency-interest mailing list (btw that’s probably the more appropriate channel for this Java-centric question).
>
> For your case, it seems like an AtomicReference<Runnable> is more appropriate.
But then I would have 2 volatile accesses instead of one
.
> terminate() sets it, then checks the count via a volatile load (or maybe it can decrement() itself?); if zero, CAS null into the action field to take/claim the action. decrement() likewise tries to claim the action via a CAS. The snippet you have now would allow for concurrent action execution, which is likely unsafe/wrong.
I don't see the difference between 2 atomics and my snippet WRT
concurrent execution.
They can both be executed concurrently with arbitrary interleaving, no?
I think my snippet is safe as long as in terminate() there is a
volatile write after setting the action (it is admittedly weird to add
zero just to obtain a memory effect, I could have used
VarHandle.releaseFence() if I were in JDK 11), since the action would
be visible from decrement() because it does a volatile read on the
same variable, no?
--
Simone Bordet
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Finally, no matter how good the architecture and design are,
to deliver bug-free software with optimal performance and reliability,
the implementation technique must be flawless. Victoria Livschitz
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On x86, I’ve never heard of failed CAS being cheaper. In theory, cache snooping can inform the core whether it’s xchg would succeed without going through the RFO dance. But, to perform the actual xchg it would need ownership regardless (if not already owned/exclusive).Sharing ordinary mutable memory isn’t scalable, forget locks :) Just doing plain loads/stores of shared memory will kill scalability (and perf) due to cache coherence traffic.ARM uses LL/SC for CAS, and is much more susceptible to failures (eg even if the value is expected, if the line has been refreshed after the LL part, it fails). But, I’m not overly familiar with ARM internals/mechanics.
On Sat, Sep 14, 2019 at 3:20 PM Francesco Nigro <nigr...@gmail.com> wrote:
Although not mentioned (neither on Doug's cookbook) I have always supposed was more likely the c++ default for both weak/strong CAS ie seq_cst memory ordering.
To make this question more mechanical sympathy focused: on hardware level what happen? I would be curious to know both x86/arm versions for this, what kind of memory reordering are guaranteed...
Most people says that a failed CAS cost much less then one that succeed, but just like a load or more?
Probably the success will cause invalidation of all the caches that reference the cache line changed, but the failed case should lock (on x86) it and AFAIK locks (hw or SW) are not well known to be scalable and performant :)
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if (ACTION.getOpaque(this) != expected) return false;
return compareAndExchange(this, expected, newValue) == expected;
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Couldn't you do a compare and compare and swap? With VarHandles something likeif (ACTION.getOpaque(this) != expected) return false;
return compareAndExchange(this, expected, newValue) == expected;
Not sure I got this correct
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