[mbedmicro/pyOCD] add support for STM32L031x6 (#520)
michieldwitte
Adds support for the STM32L031x6, tested on STM32L031K6.
Programming/reading the flash (0x8000000) and ram (0x20000000) works.
Reading the eeprom (0x08080000) works as well.
Programming the eeprom raises an exception but succeeds.
Reading the eeprom confirms the file was programmed.
Code ran:
from pyocd.core.helpers import ConnectHelper
from pyocd.core.session import Session
from pyocd.flash.loader import FileProgrammer
allProbes = ConnectHelper.get_all_connected_probes()
probe = allProbes[0]
session = Session(probe, target_override="stm32l031x6")
session.open()
FileProgrammer(session).program("/home/meechee/project/github/pyOCD/whoo.bin", base_address=0x08080000)
Output:
[---|---|---|---|---|---|---|---|---|----]
[Traceback (most recent call last):
File "/home/user/pyOCD/test/pyocd test.py", line 9, in <module>
FileProgrammer(session).program("/home/user/pyOCD/whoo.bin", base_address=0x08080000)
File "/home/user/pyOCD/pyocd/flash/loader.py", line 135, in program
self._loader.commit()
File "/home/user/pyOCD/pyocd/flash/loader.py", line 457, in commit
perf = builder.program(chip_erase=chipErase, progress_cb=self._progress_cb, fast_verify=self._trust_crc)
File "/home/user/pyOCD/pyocd/flash/flash_builder.py", line 257, in program
flash_operation = self._page_erase_program_double_buffer(progress_cb)
File "/home/user/pyOCD/pyocd/flash/flash_builder.py", line 640, in _page_erase_program_double_buffer
result = self.flash.wait_for_completion()
File "/home/user/pyOCD/pyocd/flash/flash.py", line 440, in wait_for_completion
while(self.target.get_state() == Target.TARGET_RUNNING):
File "/home/user/pyOCD/pyocd/core/coresight_target.py", line 270, in get_state
return self.selected_core.get_state()
File "/home/user/pyOCD/pyocd/coresight/cortex_m.py", line 691, in get_state
dhcsr = self.read_memory(CortexM.DHCSR)
File "/home/user/pyOCD/pyocd/coresight/cortex_m.py", line 525, in read_memory
result = self.ap.read_memory(addr, transfer_size, now)
File "/home/user/pyOCD/pyocd/probe/stlink_probe.py", line 249, in read_memory
result = conversion.byte_list_to_u32le_list(self._link.read_mem32(addr, 4, self._apsel))[0]
File "/home/user/pyOCD/pyocd/probe/stlink/stlink.py", line 272, in read_mem32
return self._read_mem(addr, size, Commands.JTAG_READMEM_32BIT, self.MAXIMUM_TRANSFER_SIZE, apsel)
File "/home/user/pyOCD/pyocd/probe/stlink/stlink.py", line 241, in _read_mem
raise STLinkException("STLink error ({}): {}".format(status, Status.MESSAGES.get(status, "Unknown error")))
pyocd.probe.stlink.STLinkException: STLink error (20): DP wait
You can view, comment on, or merge this pull request online at:
https://github.com/mbedmicro/pyOCD/pull/520
Commit Summary
- add support for STM32l031x6
File Changes
Patch Links:
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Chris Reed
@flit commented on this pull request.
In pyocd/target/target_STM32L031x6.py:
> + ) +} + + +class STM32L031x6(CoreSightTarget): + + memoryMap = MemoryMap( + FlashRegion(start=0x08000000, length=0x8000, blocksize=0x1000, is_boot_memory=True, algo=FLASH_ALGO), + RamRegion(start=0x20000000, length=0x2000), + FlashRegion(start=0x08080000, length=0x400, blocksize=0x400, algo=FLASH_ALGO) + ) + + def __init__(self, link): + super(STM32L031x6, self).__init__(link, self.memoryMap) + + def create_init_sequence(self):
You can remove the create_init_sequence() method if it doesn't modify the sequence.
But you probably want to add an init task to set the DBGMCU registers like the other STM32 targets. Otherwise timers will continue running when the core is halted, and if the chip goes to sleep the debugger connection will be lost (changed with DBG_STANDBY, DBG_STOP, and DBG_SLEEP).
Chris Reed
> + + # Flash information + 'flash_start': 0x8000000, + 'flash_size': 0x8000, + 'sector_sizes': ( + (0x0, 0x80), + ) +} + + +class STM32L031x6(CoreSightTarget): + + memoryMap = MemoryMap( + FlashRegion(start=0x08000000, length=0x8000, blocksize=0x1000, is_boot_memory=True, algo=FLASH_ALGO), + RamRegion(start=0x20000000, length=0x2000), + FlashRegion(start=0x08080000, length=0x400, blocksize=0x400, algo=FLASH_ALGO)
Could you add names to at least the flash memory regions?
Daniel Egger
I feel there should be a more generic implementation which is simply used for all compatible chips. Otherwise there'll be hundreds of files and classes all of them essentially doing the same...
michieldwitte
@michieldwitte pushed 1 commit.
- 7c763da Added initialisation of DBG_CR register, added names to flash and ram regions
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Chris Reed
I agree that would be ideal. Unfortunately, the DBGMCU APBxFZRy registers, in particular, vary considerably between different STM32 devices.
The solution is that pretty soon, pyOCD will be changing so target support primarily comes from CMSIS Device Family Packs (DFPs). The STM32 packs contain debug variables and a custom DebugCoreStart debug sequence to set the DBGMCU registers. While pyOCD won't support debug sequences right away, it will happen eventually.
michieldwitte
@michieldwitte commented on this pull request.
In pyocd/target/target_STM32L031x6.py:
> + + # Flash information + 'flash_start': 0x8000000, + 'flash_size': 0x8000, + 'sector_sizes': ( + (0x0, 0x80), + ) +} + + +class STM32L031x6(CoreSightTarget): + + memoryMap = MemoryMap( + FlashRegion(start=0x08000000, length=0x8000, blocksize=0x1000, is_boot_memory=True, algo=FLASH_ALGO), + RamRegion(start=0x20000000, length=0x2000), + FlashRegion(start=0x08080000, length=0x400, blocksize=0x400, algo=FLASH_ALGO)
Fixed in latest commit!
michieldwitte
> + ) +} + + +class STM32L031x6(CoreSightTarget): + + memoryMap = MemoryMap( + FlashRegion(start=0x08000000, length=0x8000, blocksize=0x1000, is_boot_memory=True, algo=FLASH_ALGO), + RamRegion(start=0x20000000, length=0x2000), + FlashRegion(start=0x08080000, length=0x400, blocksize=0x400, algo=FLASH_ALGO) + ) + + def __init__(self, link): + super(STM32L031x6, self).__init__(link, self.memoryMap) + + def create_init_sequence(self):
Fixed in latest commit!
Chris Reed
@flit commented on this pull request.
In pyocd/target/target_STM32L031x6.py:
> + )
+
+ def __init__(self, link):
+ super(STM32L031x6, self).__init__(link, self.memoryMap)
+
+ def create_init_sequence(self):
+ seq = super(STM32L031x6, self).create_init_sequence()
+
+ seq.insert_after('create_cores',
+ ('setup_dbgmcu', self.setup_dbgmcu)
+ )
+
+ return seq
+
+ def setup_dbgmcu(self):
+ self.write32(DBGMCU.DBG_CR, DBGMCU.DBG_CR_VALUE)
Missing newline at the end of the file. (Note the red icons.)
Chris Reed
I should also mention that the DBGMCU_CR registers are standardised, so we can create an STM32 family class that manages them for all STM32 targets (and DFP-based STM32 targets before debug sequences are supported). I've taken a note to address this.
michieldwitte
@michieldwitte pushed 1 commit.
- 429f657 added newline
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michieldwitte
@michieldwitte pushed 1 commit.
- 64af04a added debug freeze registers
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Chris Reed
@flit approved this pull request.
Thanks!
Chris Reed
/morph test
Chris Reed
Merged #520 into master.