Quadword constant

[Schmitt, Michael]

HLASM has fixed decimal constants for Halfwords, Fullwords, Doublewords, with appropriate alignment. Why is there none for Quadwords?

The closest I see is LQ, but that appears to be intended for floating point.

[Paul Gilmartin]

On Apr 18, 2022, at 09:02:41, Schmitt, Michael wrote:
>
> HLASM has fixed decimal constants for Halfwords, Fullwords, Doublewords, with appropriate alignment. Why is there none for Quadwords?
>
> The closest I see is LQ, but that appears to be intended for floating point.
>

What instructions take fixed quadword operas? I imagine some variant of
Divide.

But it becomes increasingly absurd that a 64-bit machine is supported by
only a 32-bit assembler.

--
gil

[Steve Smith]

HLASM has fixed BINARY constant type specifiers for H, F, FD. The
architecture has no support that I know of for 16-byte fixed binary, so why
should the assembler?

sas

On Mon, Apr 18, 2022 at 11:06 AM Schmitt, Michael <michael...@dxc.com>
wrote:

[Don Higgins]

>What instructions take fixed quadword operas? I imagine some variant of
Divide.

Yes, DLG and DLGR operate on 128 bit dividend in 64 bit r1 and r1+1. But
since the dividend is in registers, there is no requirement for quad word
alignment.

Don Higgins
d...@higgins.net
www.don-higgins.net

[Charles Mills]

Seems to me I ran into this issue trying to set up the parms for PLO. The
comparison and replacement values are 128 bits IIRC.

Charles

[Paul Gilmartin]

On Apr 18, 2022, at 10:03:05, Don Higgins wrote:
>
>> What instructions take fixed quadword operas? I imagine some variant of Divide.
>
> Yes, DLG and DLGR operate on 128 bit dividend in 64 bit r1 and r1+1. But
> since the dividend is in registers, there is no requirement for quad word
> alignment.
>

But there is no HLLASM construct to generate that 128-bit dividend,
Whether aligned for not. Imagine:
TERA. EQU 1000000*1000000
DIVIDEND DC AL8(TERA)

Why not?

DIVIDEND DC x'000000E8D4A51000' Hardly suffices.

> -----Original Message-----
> From: Paul Gilmartin
> Sent: Monday, April 18, 2022 11:40 AM
>

[Robin Vowels]

On 2022-04-19 02:03, Don Higgins wrote:
>> What instructions take fixed quadword operas? I imagine some variant
>> of
> Divide.
>
> Yes, DLG and DLGR operate on 128 bit dividend in 64 bit r1 and r1+1.
> But
> since the dividend is in registers, there is no requirement for quad
> word
> alignment.

He is asking, how do you a specify a decimal dividend (128 bits)
that is to be loaded into these registers?

> Don Higgins
> d...@higgins.net
> www.don-higgins.net
>
> -----Original Message-----
> From: IBM Mainframe Assembler List <ASSEMBL...@LISTSERV.UGA.EDU> On
> Behalf Of Paul Gilmartin
> Sent: Monday, April 18, 2022 11:40 AM
> To: ASSEMBL...@LISTSERV.UGA.EDU
> Subject: Re: Quadword constant
>
> On Apr 18, 2022, at 09:02:41, Schmitt, Michael wrote:
>>
>> HLASM has fixed decimal constants for Halfwords, Fullwords,
>> Doublewords,
> with appropriate alignment. Why is there none for Quadwords?
>>
>> The closest I see is LQ, but that appears to be intended for floating
> point.
>>

> What instructions take fixed quadword operands? I imagine some variant

[Seymour J Metz]

VA foo,bar,baz,4



--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3

________________________________________
From: IBM Mainframe Assembler List [ASSEMBL...@LISTSERV.UGA.EDU] on behalf of Steve Smith [sas...@GMAIL.COM]
Sent: Monday, April 18, 2022 11:41 AM

To: ASSEMBL...@LISTSERV.UGA.EDU
Subject: Re: Quadword constant

[Seymour J Metz]

It's not just DLG and DLGR, but a whole slew of vector instructions with M4=4.

--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3

________________________________________

From: IBM Mainframe Assembler List [ASSEMBL...@LISTSERV.UGA.EDU] on behalf of Paul Gilmartin [00000014e0e4a59...@LISTSERV.UGA.EDU]
Sent: Monday, April 18, 2022 11:40 AM

To: ASSEMBL...@LISTSERV.UGA.EDU
Subject: Re: Quadword constant

[Paul Gilmartin]

On Apr 18, 2022, at 16:48:23, Seymour J Metz wrote:
>
> VA foo,bar,baz,4
>
Please show how to define foo, bar, and baz with HLASM to specify
A dividend of fixed point 1E15.

Did you use a calculator?

> ________________________________________
> From: Steve Smith

> Sent: Monday, April 18, 2022 11:41 AM
>

> HLASM has fixed BINARY constant type specifiers for H, F, FD. The
> architecture has no support that I know of for 16-byte fixed binary, so why
> should the assembler?
>

The dividend for a Grande divide.

--
gil

[David Cole]

I went looking for the PDFs for the High Level Assembler and was
surprised at how hard they were to find...

I started at "z/OS Internet Library"
(https://www-40.ibm.com/servers/resourcelink/svc00100.nsf/pages/zosInternetLibrary?OpenDocument).

From there I selected "V2R3" from "Download books in PDF format".
That took me to:
https://www-40.ibm.com/servers/resourcelink/svc00100.nsf/pages/zOSV2R3Library?OpenDocument.

Then under "Elements and Features" there is a nice, pretty drop down
for "+ HLASM" which lists the "-08" editions of the Reference and
Programmer's Guide".

So far, so good.



BUT I'm looking for the new "-09" editions mentioned in APAR PH39324
(https://www.ibm.com/support/pages/apar/PH39324).

So, I tried following the same process for z/OS "V2R4" and for "V2R5",
only to discover that there is no dropdown for "+ HLASM"! WTH?????

So I have two questions:

1) Why are HLASM manuals available only if you know the secret of
looking under z/OS V2R3?
2) Where are the latest and greatest -09 editions?

I'm asking for a friend.



David Cole
President, ColeSoft

dbc...@gmail.com (personal)
dbc...@colesoft.com (business)
540-456-6518 (cell)

[Jonathan Scott]

Ref: Your note of Tue, 19 Apr 2022 05:48:37 -0400

HLASM now has its own IBM Docs site:

https://www.ibm.com/docs/en/hla-and-tf/1.6

There are links to current PDF documents from that site.

Note that documentation updates mentioned in APAR text may take
some days or weeks to appear in the IBM Docs online and PDF
formats.

Jonathan Scott, HLASM
IBM Hursley, UK

[David Cole]

Thanks John. That's helpful.

Dave

[Seymour J Metz]

VA takes three vector-register operands; it's VL that takes a storage operand.

I never claimed that HLASM supported quadword integers, just that there were more than two instructions for quadword binary integer arithmetic.

________________________________________
From: IBM Mainframe Assembler List <ASSEMBL...@LISTSERV.UGA.EDU> on behalf of Paul Gilmartin <00000014e0e4a59...@LISTSERV.UGA.EDU>
Sent: Monday, April 18, 2022 8:48 PM

To: ASSEMBL...@LISTSERV.UGA.EDU
Subject: Re: Quadword constant

On Apr 18, 2022, at 16:48:23, Seymour J Metz wrote:

[David Cole]

Thanks John. I appreciate the tips.

Best, Dave

[Bob Raicer]

A couple of more general instructions which require quadword aligned
storage operands and 128-bit values in even-odd pairs of 64-bit
GPRs:

Compare Double and Swap (CDSG)
Compare and Swap and Store (CSST)

Having the ability to assemble quadword aligned 128-bit items for
use with these instructions would be helpful.

[Ed Jaffe]

On 4/19/2022 7:13 PM, Bob Raicer wrote:
>
> Having the ability to assemble quadword aligned 128-bit items for
> use with these instructions would be helpful.

We define quadword-aligned storage areas all the time. For example:

Field1  DC LQ'0'
Field2  DC LQ'0'

Of course, you need to specify the SECTALGN option.

We align all of our sections on cache-line boundaries, but technically
you don't need more than quadword alignment to make LQ work.

--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
https://www.phoenixsoftware.com/


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[Seymour J Metz]

Yes, but I know of no way to define a quadword binary fixed point integer constant in the current HLASM.

--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3

________________________________________
From: IBM Mainframe Assembler List [ASSEMBL...@LISTSERV.UGA.EDU] on behalf of Ed Jaffe [edj...@PHOENIXSOFTWARE.COM]
Sent: Tuesday, April 19, 2022 10:22 PM

To: ASSEMBL...@LISTSERV.UGA.EDU
Subject: Re: Quadword constant

On 4/19/2022 7:13 PM, Bob Raicer wrote:
>
> Having the ability to assemble quadword aligned 128-bit items for
> use with these instructions would be helpful.

We define quadword-aligned storage areas all the time. For example:

Field1 DC LQ'0'
Field2 DC LQ'0'

Of course, you need to specify the SECTALGN option.

We align all of our sections on cache-line boundaries, but technically
you don't need more than quadword alignment to make LQ work.

--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245

https://secure-web.cisco.com/1ogePMRKwHO_SN3nXQvDcTQByAD0y_PcuSB5iExWepwkCXwevZFLD_lp5TkvnS_DPrwh9gFyyLxQKsbk50j--YszHyZVqZlyf6CzYz_ex-FTyIslsUxWo8_6zZaZRjSWoedf-eDloErk4Qs9VrSsJJzFCz5g1CmhlRBcwvAP9a6KyrvEwOMLZQy-lh8Eleg6YyRCwbuWD4QRJ4MG_-RIpJF32UQT5XbYEdjS32q7XC9l7B4Ym2p2_NCbL9H2r5zJeUYzNo-vn4FkyHeQPZHgrl2cvth1XdXDhpyeZHDfTFPyLeH9b6KKN_on3AUXeewCFZLk6-1ki6uawj_f_2UyIA9O-1J2x-0Q-zsJPbpdEe09rnM1obD0_8th4bTEGtefT9uzu5J9oFWeW7QMGO-z0I_fWx9IcIwce_dv5heMdhdw08AISIF5LzISKGOXRTl0T/https%3A%2F%2Fwww.phoenixsoftware.com%2F

[Bob Raicer]

Ed;

Of course, what you said about the LQ type of DC is true, and I too
have used LQ data types in some of my code too.  However, the
SECTALGN requirement is a bit of an issue when assembling code with
2**3 (double word) section alignment and which also contains DSECTs
which map quad word aligned storage areas.  I've had to resort to
schemes like what is shown below (I hope the list server doesn't
mangle the sample listing too badly).

The reason(s) for still having double word aligned sections is (are)
a bit lost in antiquity -- inertia is a powerful thing :)

: D-Loc   Object Code     Stmt   Source Statement
:00000000                    1 SAMPLE   DSECT ,
:                            2          PRINT ON,DATA
:00000000 00000010           3 REF      DC    A(QUADITEM)
:00000004 00                 4 BYTE     DC    AL1(0)
:                            5 * ---------------------------------------------------------
:00000005 0000000000000000   6          DC (((((*-SAMPLE)+15)/16)*16)-(*-SAMPLE))AL1(0)
:0000000D 000000
:                            7 * Round up to a Quad Word
:                            8 * boundary.
:                            9 *
:00000010 0000000000000000  10 QUADITEM DC    XL16'00'
:00000018 0000000000000000
:                           11          END   ,

[Steve Smith]

That's the old-fashioned way. This is the new way:

USING *,16

There are some caveats. For CSECTs, HLASM will complain if SECALGN is
insufficient. For DSECTs, it's your responsibility to ensure the alignment
matches (if it's real important). Fortunately, STORAGE has a corresponding
alignment specification.

sas

[Steve Smith]

Sheesh. Sorry, I meant ORG *,16.

[Charles Mills]

I was wondering about R16. Would come in handy.

Charles

-----Original Message-----
From: IBM Mainframe Assembler List [mailto:ASSEMBL...@LISTSERV.UGA.EDU] On Behalf Of Steve Smith
Sent: Wednesday, April 20, 2022 9:31 AM
To: ASSEMBL...@LISTSERV.UGA.EDU
Subject: Re: Quadword constant

[Tony Harminc]

On Wed, 20 Apr 2022 at 13:03, Charles Mills <char...@mcn.org> wrote:

> > USING *,16

> I was wondering about R16. Would come in handy.

Maybe on the z16...?

[There was an old PL/I Optimizer APAR (1980ish?) complaining that a
new compiler release could not generate code for certain large source
modules that had worked previously. The IBM answer was that there
weren't enough registers, and that if that were to be addressed in a
future hardware version, then they'd be able to generate larger code
blocks. Of course in a sense the compiler folks eventually got what
they wanted in the High-Word Facility on zArch.]

Tony H.

[Bob Raicer]

---------  begin snippet (from Steve Smith)

That's the old-fashioned way.  This is the new way:

        ORG *,16
---------  end snippet

The assembler still cares about SECTALGN.  The "old fashioned way"
works fine, independent of SECTALGN.  Also, note that I explicitly
stated mapping quad word aligned storage areas, which, as you and
others have noted, can be easily obtained using STORAGE
OBTAIN,STARTBDY=4 (and other methods, such as the various Cell Pool
services).

With respect to ensuring "the alignment matches", it pretty much is
always important (I'm sure that you could come up with some use case
where you intentionally want a mismatch of the alignment).

[Jonathan Scott]

Since APAR PH40885 you can simply suppress warning ASMA500W if
you don't want to be nagged about item alignment exceeding
SECTALGN, as the alignment warning no longer prevents the
expected code from being generated.

The section alignment for purposes of code generation is now
always assumed to be as strong as is needed, but the binder
alignment option is set based on SECTALGN and the warning is
issued if item alignment exceeds the binder section alignment.

[Schmitt, Michael]

Today I learned that there isn't a fixed point DOUBLEWORD constant either.

I never noticed that DC D isn't fixed point, it is floating point.

-----Original Message-----
From: IBM Mainframe Assembler List <ASSEMBL...@LISTSERV.UGA.EDU> On Behalf Of Schmitt, Michael
Sent: Monday, April 18, 2022 10:03 AM
To: ASSEMBL...@LISTSERV.UGA.EDU

[Ngan, Robert (DXC Luxoft)]

FD is a fixed point doubleword.

Robert Ngan
DXC Luxoft

-----Original Message-----
From: IBM Mainframe Assembler List <ASSEMBL...@LISTSERV.UGA.EDU> On Behalf Of Schmitt, Michael

Sent: Thursday, May 19, 2022 13:09
To: ASSEMBL...@LISTSERV.UGA.EDU
Subject: Re: Quadword constant

[Paul Gilmartin]

On May 19, 2022, at 12:16:45, Ngan, Robert (DXC Luxoft) wrote:
>
> FD is a fixed point doubleword.
>

Alas, there's no way to define a doubleword constant containing the
value of an arithmetic expression AL8(2+2)?

Having only a 32-bit assembler for a 64-bit architecture is
increasingly becoming anachronistic.

> -----Original Message-----
> From: Schmitt, Michael
> Sent: Thursday, May 19, 2022 13:09
>

> Today I learned that there isn't a fixed point DOUBLEWORD constant either.
>
> I never noticed that DC D isn't fixed point, it is floating point.
>
>
> -----Original Message-----
> From: Schmitt, Michael
> Sent: Monday, April 18, 2022 10:03 AM
>

> HLASM has fixed decimal constants for Halfwords, Fullwords, Doublewords, with appropriate alignment. Why is there none for Quadwords?
>
> The closest I see is LQ, but that appears to be intended for floating point.

--
gil

[Ngan, Robert (DXC Luxoft)]

However, AD(2+2) works fine
As long as the expression does not exceed a 32-bit signed value. Yes, it would be very useful if HLASM could resolve 64-bit arithmetic expressions, and it's a PITA that it doesn't.

Robert

-----Original Message-----
From: IBM Mainframe Assembler List <ASSEMBL...@LISTSERV.UGA.EDU> On Behalf Of Paul Gilmartin
Sent: Thursday, May 19, 2022 14:49
To: ASSEMBL...@LISTSERV.UGA.EDU
Subject: Re: Quadword constant

[Steve Smith]

AD

This isn't new.

sas

[Paul Gilmartin]

> On May 19, 2022, at 14:39:49, Steve Smith wrote:
>
> AD
>
> This isn't new.
>

DC AD(1000000*1000000)
???

> On Thu, May 19, 2022 at 3:49 PM Paul Gilmartin wrote:
>> On May 19, 2022, at 12:16:45, Ngan, Robert (DXC Luxoft) wrote:
>>>
>>> FD is a fixed point doubleword.
>>>
>> Alas, there's no way to define a doubleword constant containing the
>> value of an arithmetic expression AL8(2+2)?
>>
>> Having only a 32-bit assembler for a 64-bit architecture is
>> increasingly becoming anachronistic.

--
gil

[Steve Smith]

If you have more than an academic interest, there's always RFE, also not
new. In my limited world, the need for writing constants > 2G has not
really come up much.

The famous =FDS12E6'1' is about it, and already works (one second in TOD
format; multiples, up to a few hours at least, also work).

sas

[Abe Kornelis]

All,

for literals where the assembler refuses to do the calculus for you,
you can use a SETA statement to determine the value,
then use the SETA symbol to promote the calculated value into the DC value.

The upper limit of 2G of results, including any intermediate values,
still applies.
To get around that you'll need to work out the SETA for a set of variables
holding sections of the final number. Clunky, but it can be made to work.

Success!
Abe
===


Op 19/05/2022 om 21:48 schreef Paul Gilmartin: