Macsim Developer

Do you have the trace file of spec06 benchmark? I would appreciate it if you could write back.

Hi all, I've been working on cache partitioning algorithms. But I don't know how to realize

Hello Rahul, We might still have some traces for public access. We used to have some hosted

Hi Adhar, I haven't worked with TLB in macsim before. Hyojong (cc'ed) has done some work,

Hi, I am a student of Indian Institute Of Technology , Madras. I was trying to use macsim for one of

Have you released Intel GPU traces of various workloads from Intel OpenCL samples and Rodinia

Hi, Hyesoon, I am new to gpuocelot, and I have installed the gpuocelot in my ubuntu pc. I want to

hey davesh can i have your mail id for contact. please send your mail id.

Hi all, I am new to macsim. I am trying to generate x86 trace files. I am using pin2.14 version. I am

Hello, Currently, I am studying hardware simulation. And I am learning about Macsim to see if I can

Hi All, I am new to using mac-sim. I am using the trace_reader tool to splice up a raw trace file (

Hi, As follow up to the above issue, I tried running 1c1g simulations with the two traces given with

Hi manager, I try to put the macsim into the SST (sst 6.1.0), but with many errors. which file I

MacSim have features to change frequency so it can simulate DVFS. Are you using just MacSim stand

Hi, While working with the Macsim simulator, I encountered a possible bug in memory.cc . It is

DRAMSim library is created in .opt_build or .dbg_build directory. You can add the following

Hello sir, I'm also facing the same problem in building macsim with dram, did you found any

Hi, It seems DRAM2.h and Addressmapping.h are missing in the sst/elements/VaultSimc... Can I use the

I think I made you confused. Macsim doesn't do address translation. It just change some upper

Dear Professor Hyesoon, I have reduced the cache size, but the network injection rate is still low. I

First, max num core per appl means how many applications per core not how many cores per application.

You could modify trace generator to collect only ld/st Or you could modify trace read cpu.cc to

Thank you for your help. Now I have another question. I only use the macsim. the number of cpu is 4

For bzip2 or other spec benchmarks, you don't need to provide “-thread 2” option. In that case it

Yes, I am looking at OpenGL applications, not OpenCL applications. -Akhila On Wed, Sep 23, 2015 at 9:

Hello Hsing-Min, I am glad to hear it. Let me know if you have any difficulties in using MacSim.

Hi Namhyung, We are currently working on using a newer version of Ocelot and updating a trace version

This problem is typically caused by using mis-matched version of traces. Please make it sure you are

Hi, When you run 4 cores, all cores are sharing the memory system especially DRAM, so there should be

Hi Ankul, Perhaps you may have resolved the issue. I had a similar issue. The segfault for me