Registers X64

[Jarrell Campbell]

Aprocessor register is a quickly accessible location available to a computer's processor.[1] Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. In computer architecture, registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900.[2]

Almost all computers, whether load/store architecture or not, load items of data from a larger memory into registers where they are used for arithmetic operations, bitwise operations, and other operations, and are manipulated or tested by machine instructions. Manipulated items are then often stored back to main memory, either by the same instruction or by a subsequent one. Modern processors use either static or dynamic RAM as main memory, with the latter usually accessed via one or more cache levels.

Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access data. The term normally refers only to the group of registers that are directly encoded as part of an instruction, as defined by the instruction set. However, modern high-performance CPUs often have duplicates of these "architectural registers" in order to improve performance via register renaming, allowing parallel and speculative execution. Modern x86 design acquired these techniques around 1995 with the releases of Pentium Pro, Cyrix 6x86, Nx586, and AMD K5.

When a computer program accesses the same data repeatedly, this is called locality of reference. Holding frequently used values in registers can be critical to a program's performance. Register allocation is performed either by a compiler in the code generation phase, or manually by an assembly language programmer.

Registers are normally measured by the number of bits they can hold, for example, an "8-bit register", "32-bit register", "64-bit register", or even more. In some instruction sets, the registers can operate in various modes, breaking down their storage memory into smaller parts (32-bit into four 8-bit ones, for instance) to which multiple data (vector, or one-dimensional array of data) can be loaded and operated upon at the same time. Typically it is implemented by adding extra registers that map their memory into a larger register. Processors that have the ability to execute single instructions on multiple data are called vector processors.

In some architectures (such as SPARC and MIPS), the first or last register in the integer register file is a pseudo-register in that it is hardwired to always return zero when read (mostly to simplify indexing modes), and it cannot be overwritten. In Alpha, this is also done for the floating-point register file. As a result of this, register files are commonly quoted as having one register more than how many of them are actually usable; for example, 32 registers are quoted when only 31 of them fit within the above definition of a register.

The following table shows the number of registers in several mainstream CPU architectures. Note that in x86-compatible processors, the stack pointer (ESP) is counted as an integer register, even though there are a limited number of instructions that may be used to operate on its contents. Similar caveats apply to most architectures.

Although all of the below-listed architectures are different, almost all are in a basic arrangement known as the von Neumann architecture, first proposed by the Hungarian-American mathematician John von Neumann. It is also noteworthy that the number of registers on GPUs is much higher than that on CPUs.

The number of registers available on a processor and the operations that can be performed using those registers has a significant impact on the efficiency of code generated by optimizing compilers. The Strahler number of an expression tree gives the minimum number of registers required to evaluate that expression tree.

While trying to articulate and justify this notion of natural analogies between these features, andthe notion that each of them is incomplete, I developed an idea that I think is more generallyuseful, and that is the notion of programming language registers.

Programming languages are similar. When writing a piece of code, even with the language selectionmade and the intended effect understood, the user must also select the register they will use. InRust, this distinction in register can look like this:

Each of these registers has a use case to which it is particularly well suited. Implementing futuresby hand has a high cognitive burden (and requires careful consideration of potential bugs) but givesthe user greater control; it is suited for specific use cases which are fundamental to the ecosystemor in which the user cares a great deal about control.

Some cells are just exempli gratis - there are more methods that consume on iterator for examplethan just collect - but the pattern is clear to see. If a method returns the reified type again, itis in the combinatoric register, whereas if it consumes it and returns something else, it is in theconsuming register. And while some cells are missing for asynchrony, they are provided by thirdparty libraries - the consuming register (spawn and block_on) being the most obviously critical andthe one the project has most frequently considered how to bring into the standard library.

When considering iteration, the user is faced with a dilemma. The two obvious and easy ways toperform iteration are the consuming and combinatoric register. And indeed, these adequately coverthe large majority of cases. But there is a case in which users are often stuck between them,switching back and forth unhappily, because the control-flow register is absent.

Specifically, users might want to abstract a particular iterative operation into a function withoutleaving the effect. This was one of the main motivations for stabilizing -> impl Iterator. But inorder to do that, they must use combinators. And here they run into an issue: it can be quitedifficult to construct complex control flow paths with combinators. Users often have the experienceof finding this inadequate, and realizing they will be better off using a for loop. In the worstcase, what users end up doing is collecting into an intermediate allocation, only to immediatelybegin iterating over that again, because trying to structure their code with combinators is eitherimpossible or renders it unreadable.

A specific case of this problem is when users want to combine effects - for example they want to mapa fallible function over an Iterator, or map an asynchronous function over a Result. In some casesthis is possible with some contortion (for example, now you have an iterator of Results, and youneed in each subsequent combinator to short circuit on the error case), in other cases its fullyimpossible.

One essential aspect of the design is that it must be possible to combine different control floweffects in one piece of code. Asynchronous and iterative code is often fallible, for example, and wehave an easy way of handling that in the type system by creating Futures and Iterators of Results orOptions. But combining the asynchronous and iterative effects is not so trivial.

If the project pursues this path, the problem will emerge that users have no core register for theasynchrony effect of an AsyncIterator. If they need the fine-grained control the core registerprovides them, they will be left with no options. For a systems language this is fully inadequate.But if poll_next stays, then there is a core register for the combination of asynchrony anditeration. And if generators are added to the language, they can be made async just as well asnormal functions can - and an async generator would compile to an AsyncIterator, written fully inthe control-flow register rather than halfway.

When we look at these four register, a sort of pattern of use emerges, which informs whichregister to use. The core register is the verbose and possibly difficult to use, but it gives usersthe most absolute control. The trade off is clear. The consuming register is necessary for settingboundaries on the effect. But when it comes to the combinatoric and control-flow register, we areleft with a question: what is really the difference between them? Both are touted as easy ways toachieve the end result. Both involve the acceptance of abstraction by the user (and thus the loss ofexplicit control over layout) as the trade off for getting things done. But what is the distinctionbetween them?

One obvious distinction between them is that one is written in an imperative style (control flow)and one is written in a functional style (combinatoric). Similarly, one is more naturally suited toblocks of statements (control flow) and one is more naturally suited to an expression-orientedprogramming (combinatoric), though neither completely excludes either way of writing. Indeed, tosome extent the difference between these two registers might be paradigmatic and stylistic. Rust isa multi-paradigm language after all.

But I find, in my own experience, that too complicated an assemblage of combinators can negativelyimpact readability. There is a subjective limit below which writing in the combinatoric style makescode clearer, and above which it makes it less clear.

This blog post has already gotten quite long and in that last section I verged on opening a real canof worms: keyword generics. I think this is enough for now. If I successfully continue to write inthe near future, I will open with that discussion next time.

I really hope this framework of registers and control-flow effects will resonate with others, andcan provide guidance for disentangling the design questions that face Rust today. But even if youthink this particular application has some fatal flaw, I hope the concept of registers can be moregenerally useful to everyone trying to design and analyze programming languages.

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